66AK2G12: 66AK2G12, EMIF /DDR interface , FPGA

Hi again,

I would not say that's impossible as I just don't know that. What I know is that intended high speed link to FPGA is PCIe. With that one still can use DDR RAM as a pocket buffer between DSP and FPGA. On DSP side there is DMA, namely EDMA3 engine to perform data moves without CPU intervention. Particularly, it can be instructed to fetch data out of FPGA to desired location. Bear in mind, that would require FPGA design to be capable to handle multi-DWORD TLPs over PCIe, which may cost some efforts to your FPGA designer. Another possibility is to have DMA engine on FPGA side along with bus mastering capability. Then FPGA may push data to DSP's memory on its own. We used the latter approach for a while but dropped in favour of the former one.