66AK2G12: 66AK2G12, FPGA , PCIe interface

Hello!

The first point is about clock from FPGA towards K2 SoC, you don't really want that. Your processor device requires high quality clock to be supplied directly from clock generator or distributor. Forwarding it through FPGA is not feasible. PCIe by itself needs only reference clock, like 100MHz, though other frequencies are possible too. Then PCIe block derives its high speed clock for serial link. Note, that each receiver recovers incoming clock from data, i.e. when processors sends to FPGA, FPGA's PCIe block on receiver side recovers clock out of data. Similarly, when FPGA sends towards DSP, PCIe subsystem on processor side recovers incoming clock from serial link. Nevertheless, it is recommended that reference clock of both parties was synchronous, i.e. produced by same source.

Second, PCIe data signals are low voltage differential, they obey different spec rather than 1.8 or 3.3 CMOS. So definitely there will be no level translators on serial link. However, FPGA needs reference clock and system reset signals, which may come at unavailable level. For reset use of level translator is recommended practice. If you don't mind share what is your FPGA maybe someone would tell more.

Finally, 66 MHz seems unusual reference clock for PCIe, we'd better know what is that FPGA. You may want to see Figure 11-1090 in SPRUHY8H and clause 11.14.4.7 Clock Control in the same TRM.

Hope this helps.

Hi again,

I've just checked with Xilinx Artix-7, it accepts either 100 MHz of 250 MHz as reference clock, pretty much same with other Xilinx families. K2 SoC accepts only 100 MHz. So again,it looks a bit suspicious your FPGA is taking 66 MHz as reference clock.

Hello!

As to reference clock TRM recommends both PCIe parties clocked from same source. We have operational design where reference clocks come to FPGA and DSP from different clock generators. It's up to you to find out whether FPGA derived clock will do the job.

You're correct that for reference clock I/O voltage is 1.8V, so if you can't match that from FPGA, that is yet another reason not to do so. Instead, you may want to use something like CDCM6208, which have controlled output voltage.

As for reference clock speed, let me reassure you, Spartan 6 of LXT series takes reference clock of either 100MHz or 125MHz., but not 66MHz. You may confuse PCIe transaction interface in FPGA, which again runs at 62.5MHz.

Also note, LX devices have neither PCIe hard block, nor GTP transceivers, so you can't make PCIe on LX devices. For PCIe you'll definitely need LXT device.

Considering alternatives to PCIe keep in mind, that PCIe is designed to provide addressing. You may opt for Gigabit Ethernet, however, it this case packetising and addressing will be your job. There is no Ethernet in LX devices.

There is yet another alternative as GPMC. With it you may have parallel type of interface, which probably is the easiest thing, but it is no way high speed interface. We know nothing about your target application, and device you selected for FPGA is again a bit confusing. On one hand, it's a largest 150K cell device, on another - it is in rather small 484 package. So you have to check whether you have enough pins to implement parallel interface. Keep in mind, GPMC is just 16-bit wide.