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Tool/software: Code Composer Studio
Hi,
We have made custom board out of 66AK2G12ABY100GS. In which 10 board out of 50 is facing DDR issue. We are running processor SDK version processor_sdk_rtos_k2g-hs_5_01_00_11 and PDK version : pdk_k2g-hs_1_0_11. Secure package version : proc-sdk-secdev_01_06_00_01
After flashing same image on both the boards, we ran DDR test to read and write a pattern into 0x80000000 till some size in DSP side. While reading back, we get following error in non-working board:
"C66xx: Trouble Reading Memory Block at 0x80000000 on Page 0 of Length 0x4: (Error -1202 @ 0x80000000) Device core is hung. The debugger will attempt to force the device to a ready state to recover debug "
We thought of debugging further by looking into DDR_PHY, EMIF and BOOTCFG registers, using JTAG:
1. BOOTCFG_DDR3A_PLL_CTL0 and BOOTCFG_DDR3A_PLL_CTL1 register value same as working .
2. DDR_PHY values were also same.
3. When we tried to read EMIF Registers in non working board, we found that we are not able to access the EMIF registers. We get the following error:
Trouble Reading Memory Block at 0x121010004 on Page 0 of Length 0x4: (Error -1202 @ 0x800FFFF) Device core is hung. The debugger will attempt to force the device to a ready state to recover debug control. Your application's state will be corrupt. You should have limited access to memory and registers, but you may need to reset the device to debug further.(Emulation package 8.1.0.00012)
We went and checked the XMC register to see if there is memory extension and permission set correctly for EMIF register extension and it looks to be fine and same as working board.
Looks like we are not able to access any extended addresses. When we read the alias address 0x21010000 of EMIF, we get garbage values in both working and non working boards.
1. What could be the reason for not able to access the internal EMIF registers from DSP ?
2. Any pointers to debug this issue further?
3. What hardware change that could cause such an issue of not able access only EMIF registers within SoC ? As said earlier, code is the same in both working and non-working Board.
Thanks in advance.
Sanny,
Can you access the registers from the A15 or is the issue only found on the C66x? Can you confirm if the EMIF timing is configured by the ARM or the DSP ?
There is a similar issue reported here with DDR access, can you please check the Fixed read Latency bit (FXDLAT) in PGCR2 register and let us know if that is enabled or disabled.
https://e2e.ti.com/support/processors/f/791/t/479949?Trouble-reading-DDR3-memory-location-66AK2E05
Does this only occur with boot or can you also confirm that you see the issue when initializing DDR using GEL file in CCS