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66AK2G12: Fail to DDR memory test and no DDR_CLKOUT clock output

Sung-IL
Mastermind 29840 points
Part Number: 66AK2G12

Dear Champs,

I failed to DDR memory test and failed to access DDR memory.

Could you please check below customer's schematic DDR part?

GEL file I used is almost same with EVM's.

the blow is the error msg when I tried DDR3 memory test.

~~~~~`

CortexA15: Trouble Reading Memory Block at 0x80000000 on Page 0 of Length 0x4: (Error -1205 @ 0x80000000) Device memory bus has an error and may be hung. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.576.0)
ddr3_write_read_test() cannot be evaluated.
Target failed to read 0x80000000
at temp=(ptr)[i] [evmk2g_arm.gel:1973]
at ddr3_memory_test() [evmk2g_arm.gel:2611]
at ddr3_write_read_test()CortexA15: Trouble Reading Register REG_SYSTEM_TARGET_CONFIG: (Error -1141 @ 0x3D58) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.576.0)
CortexA15: Trouble Reading Register REG_SYSTEM_MMU_CONFIG: (Error -1141 @ 0x3D58) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.576.0)
CortexA15: Trouble Reading Register REG_SYSTEM_MMU_STATUS: (Error -1141 @ 0x3D58) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.576.0)
CortexA15: Trouble Reading Register REG_SYSTEM_MMU_STATUS: (Error -1141 @ 0x3D58) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.576.0)
CortexA15: Trouble Reading Register CP15_Registers.REG_CTXA15_CP15_C2_TTBCR: (Error -1141 @ 0x3D58) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.576.0)
CortexA15: Trouble Reading Register CP15_Registers.REG_CTXA15_CP15_C2_TTBR0_64B: (Error -1141 @ 0x3D58) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.576.0)
CortexA15: Trouble Reading Register CP15_Registers.REG_CTXA15_CP15_C2_TTBR1_64B: (Error -1141 @ 0x3D58) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.576.0)
CortexA15: Trouble Reading Register CP15_Registers.REG_CTXA15_CP15_C3_DACR: (Error -1141 @ 0x3D58) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.576.0)
CortexA15: Trouble Reading Register REG_SYSTEM_MMU_STATUS: (Error -1141 @ 0x3D58) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.576.0)
CortexA15: Trouble Reading Register REG_SYSTEM_MMU_STATUS: (Error -1141 @ 0x3D58) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.576.0)
CortexA15: Trouble Reading Register CP15_Registers.REG_CTXA15_CP15_C2_TTBCR: (Error -1141 @ 0x3D58) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.576.0)
CortexA15: Trouble Reading Register CP15_Registers.REG_CTXA15_CP15_C2_TTBR0_64B: (Error -1141 @ 0x3D58) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.576.0)
CortexA15: Trouble Reading Register CP15_Registers.REG_CTXA15_CP15_C2_TTBR1_64B: (Error -1141 @ 0x3D58) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.576.0)
CortexA15: Trouble Reading Register CP15_Registers.REG_CTXA15_CP15_C3_DACR: (Error -1141 @ 0x3D58) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.576.0)

~~~~~~~~

DDR_RESET should be directly connected between K2G and DDR3 with the addition of pulled-down resister, right?

I captured from K2G schematic guide.

But, when I checked GP EVM schematic, it seemed DDR_RESET was connected with pull-up resister as below and I'm confused. Could you please make clarify on this?

Thanks and Best Regards,

SI.

  • 0
    TI__Guru**** 161600 points
    Hi,

    The design team is notified. They will post their feedback directly here.

    Best Regards,
    Yordan
  • 0
    TI__Mastermind 42545 points
    Hi Sung-IL,
    It is very difficult to determine what the issue is based on a few pieces of the schematics but let me ask a few questions.
    1) It appears from the schematic pieces that the VTT termination for the control signals is bypassed to 1.35V instead of ground. Was that done intentionally?
    2) Did you follow all the routing guidelines for length matching and impedance for the DDR signals provided in the TRM and DM for the K2G?
    3) Have you checked to be sure that all voltages are present and within tolerance. Are they sequencing in the correct order?
    4) Have you checked to be sure that the clock specified for the input to the DDR PLL is present and is providing the correct frequency?

    The pull down on the DDR reset is recommended for most designs to ensure that the DDR memories are held in reset when the SoC is not actively driving it high. For the EVM we chose to pull the reset line high to allow testing of some SoC low power modes where the DDR maintains it's contents in a self-refresh mode. Pulling the DDR reset low shouldn't cause any change in behavior.

    There are two very good documents for DDR initialization for KeyStone 2 devices. Take a look at the following and see they can provide additional help.
    www.ti.com/.../sprac04
    www.ti.com/.../sprabx7

    Regards,
    Bill
  • 0 in reply to Bill Taboada
    TI__Mastermind 29840 points
    Hi Bill,

    1) even after they changed VTT termination to GND, same error was occurred.
    2) for routing guidelines, they overlapped DDR patterns of ICE EVM PCB GERBER and they matched impedance with 100ohm for clock and 50ohm for signal.
    3) For voltage tolerance, they confirmed all voltages are present within tolerance and sequencing in the correct order.
    4) They found 48Mhz was output in the DDRCLKOUT(AE15, AD15) pins of 66AK2G12.



    Thanks and Best Regards,
    SI.
  • 0 in reply to Sung-IL
    TI__Mastermind 29840 points

    We resolved this issue. We can access DDR3 memory using ICE_EVM.gel file, and it seemed the issue was occurred as they tried to access MSB 16bits which is no DDR memory connected. There is only 1 x 16bits memory connected in my customer's board same as ICE EVM, but we used GPEVM GEL file which enabled 32bit DDR3 memory i/f.

    Thanks for your response and providing comments.

    Thanks and Best Regards,
    SI.

  • 0 in reply to Sung-IL
    TI__Mastermind 42545 points
    Hi Sung-IL,
    I'm glad the customer was able to resolve their issue. Let me know if they encounter any additional problems.
    Regards, Bill