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TDA4VE-Q1: when boot the tda4ve board, the ddr only work in ddr rate 1200, how can we change the ddr parameters to increase the ddr rate

Dao Xia
Prodigy 10 points
Part Number: TDA4VE-Q1
Other Parts Discussed in Thread: TDA4VM

Dear TI experts,

     we got a problem when boot the tda4ve board, the ddr init failed!

    we used samsung ddr K4FBE3D4HB-KHCL, we used the SPRACU8B_Jacinto7_DDRSS_RegConfigTool.xlsb tool to change the parameters, if we set the ddr rate to 3733, the ddr init failed, 

the uboot log like below:

U-Boot SPL 2021.01-dirty (Jul 20 2023 - 16:08:43 +0800)
ti_sci system-controller@44083000: Message not acknowledgedti_sci system-controller@44083000: Message no)
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
k3_ddrss_probe(dev=41c6771c) name memorycontroller@2990000
--->>> k3_lpddr4_read_ddr_type: 203 ... 0x000b<<<---
--->>> k3_ddrss_init_freq: 283 ... ddr_freq0:27500000<<<---
--->>> k3_lpddr4_start: 551 ... <<<---
--->>> LPDDR4 Initialization is in progress ... <<<---
--->>> k3_lpddr4_read_ddr_type: 203 ... 0x000b<<<---
--->>> k3_lpddr4_freq_update: 245 ...<<<---
--->>> lpddr4_startsequencecontroller: 114 ...<<<---

when we config the data rate to 1200 , the board boot successfully

but we need to change the below register in file (k3-j721s2-ddr-evm-lp4-1200.dtsi) mannually 

DDRSS0_PHY_1303_DATA 0x00000064 -> 0x0000FFFF 

DDRSS1_PHY_1303_DATA 0x00000064 -> 0x0000FFFF

we also used the tda4vm_lp4_debug.out to test the ddr ,we attach the log file (ccs-ddr-3733-072001.txt) below

Can you help us to figure out how can we increase the DDR rate,

 SDK : ti-processor-sdk-linux-j721s2-evm-08_06_01_02

SPRACU8B_Jacinto7_DDRSS_RegConfigTool parameters:

ccs-ddr-3733-072001.txt
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[MCU_Cortex_R5_0] Training Results; Frequency 0; CS 0
PHY Vref Training:
DQ Lane 0 Vref Mode: 0x7 Vref Sel: 0x2b
DQ Lane 1 Vref Mode: 0x7 Vref Sel: 0x2b
DQ Lane 2 Vref Mode: 0x7 Vref Sel: 0x2b
DQ Lane 3 Vref Mode: 0x7 Vref Sel: 0x2b
ACC Vref Control: 0x7ab
CA Training:
LP4 CA Programmed Delays:
CA Bit 0 delay: 680
CA Bit 1 delay: 680
CA Bit 2 delay: 680
CA Bit 3 delay: 680
CA Bit 4 delay: 680
CA Bit 5 delay: 680
Write Leveling:
DQ Lane 0 WRDQS: 0x28
DQ Lane 1 WRDQS: 0x1ec
DQ Lane 2 WRDQS: 0x1e8
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