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J721S2XSOMXEVM: TDA4VE: How to change DDR size?

xie jc
Expert 1970 points
Part Number: J721S2XSOMXEVM

Hi, TI engineers,

We would like to modify the DDR size on the J721S2EVM board, changing DDRSS0 to 1GB and DDRSS1 to 2GB. Is there a way to achieve this?

We are using SBL HLOS boot mode now.

Our SDK version:

RTOS: 8.06.01

LINUX: 8.06.01

Regards,

Tahm

  • 0
    TI__Guru* 81806 points

    Hello Tahm,

    You could refer the below FAQ for the change

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1227640/faq-tda4vm-tda4vl-tda4al-tda4vh-dra821-how-can-we-make-the-jacinto-sdk-compatible-for-device-variants#:~:text=for%20SDK%208.6-,1.%C2%A0Reduction%20in%20the%20number%20of%20DDR%20Instances,-Some%20of%20the

    You could skip the changes in the SBL as you still have 2 DDR memory controller instances being used. You could check the Linux changes required to modify the DDR size

    Regards,

    Nikhil

  • 0 in reply to Nikhil Dasan
    Expert 1970 points

    Hi, Nikhil,

    I try to modify the dts  k3-j721s2-som-p0.dtsi

    "

    reg = <0x00 0x80000000 0x00 0x80000000>,
    - <0x08 0x80000000 0x03 0x80000000>;
    + <0x08 0x80000000 0x01 0x80000000>;

    "

    and build the dtb, cp k3-j721s2-common-proc-board.dtb to rootfs/boot

    but the ddr size still 16GB on EVM. 

    Regards.

  • 0 in reply to xie jc
    TI__Guru* 81806 points

    Hi,

    May I know how are you checking DDR size on EVM?

    In SBL boot mode, are you using the optimized HLOS boot mode?

    xie jc said:
    cp k3-j721s2-common-proc-board.dtb to rootfs/boot

    Also, in case of SBL boot mode, if you are using combined app method, then you would have to point the dtb in the config.mk and rebuild the combined app.
    It wouldn't take it from rootfs/boot

    Regards,

    Nikhil

  • 0 in reply to Nikhil Dasan
    Expert 1970 points

    Hi, Nikhil,


    We plan to incorporate TDA4VE into our new project, but our own board has not been manufactured yet. Therefore, we are conducting preliminary research on how to use it with the EVM board.

    We are currently utilizing a development HLOS boot process. The boot sequence involves SBL initiating mcu1_0 and u-boot-spl.bin, which then launches Linux. It is not SBL directly booting the kernel.

    In our new project, we intend to connect a 1GB DDR chip to DDRSS0 and a 2GB DDR chip to DDRSS1. Our primary focus right now is to confirm the correct modifications needed. We appreciate your attention and support.

    I have made modifications to U-Boot and the kernel based on your previous responses. The modifications are as follows:

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1224003/faq-tda4vl-q1-how-to-configure-ddr-size-of-4gb-in-the-j721s2-sdk?tisearch=e2e-sitesearch&keymatch=ddr%2520size#

    boot log: 

    MobaXterm_COM5ProlificUSB-to-SerialCommPortCOM5_20230927_170938.txt
    Fullscreen
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    NOTICE: BL31: v2.7(release):v2.7.0-359-g1309c6c805-dirty
    NOTICE: BL31: Built : 22:51:35, Jan 6 2023
    I/TC:
    I/TC: OP-TEE version: 3.19.0-15-gd6c5d0037 (gcc version 9.2.1 20191025 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10))) #1 Fri Jan 6 22:51:37 UTC 2023 aarch64
    I/TC: WARNING: This OP-TEE configuration might be insecure!
    I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
    I/TC: Primary CPU initializing
    I/TC: SYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.3--1-g2249f (Chill Capybara')
    I/TC: HUK Initialized
    I/TC: Activated SA2UL device
    I/TC: Fixing SA2UL firewall owner for GP device
    I/TC: Enabled firewalls for SA2UL TRNG device
    I/TC: SA2UL TRNG initialized
    I/TC: SA2UL Drivers initialized
    I/TC: Primary CPU switching to normal world boot
    U-Boot SPL 2021.01 MV_BUILD_TAG: 6c2cb5cf7 (Sep 26 2023 - 14:58:49 +0800)
    ti_sci system-controller@44083000: Message not acknowledgedti_sci system-controller@44083000: Message not acknowledgedSYSFW ABI: 3.1 (firmware rev 0x0008 '8.6.3--1-g2249f (Chill Capybara')
    ti_i2c_eeprom_am6_parse_record: Ignoring record id 17
    ti_i2c_eeprom_am6_parse_record: Ignoring record id 17
    Trying to boot from MMC2
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX


    U-Boot 2021.01 MV_BUILD_TAG: d5792b2035-dirty (Sep 27 2023 - 16:46:03 +0800)

    SoC: J721S2 SR1.0 GP
    Model: Texas Instruments J721S2 EVM
    Board: J721S2X-PM1-SOM rev E2
    DRAM: 3 GiB
    Flash: 0 Bytes
    MMC: mmc@4f80000: 0, mmc@4fb0000: 1
    In: serial@2880000
    Out: serial@2880000
    Err: serial@2880000
    am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA02102 cpsw_ver: 0x6BA82102 ale_ver: 0x00293904 Ports:1 mdio_freq:1000000
    Net: eth0: ethernet@46000000port@1
    Hit any key to stop autoboot: 0
    mv_info: do_checkout_bootmedia:470: boot from SD card
    switch to partitions #0, OK
    mmc1 is current device
    SD/MMC found on device 1

    I feel that there might be a need to make modifications within the SBL, but I'm unsure about how to proceed. Can you provide some guidance?

    Additionally, our plan is to wait until the board is produced and then reconfigure the DDR parameters using DDRSS tools.

    Best Regards.


    Tahm

  • 0 in reply to xie jc
    TI__Guru* 81806 points

    Hi Tahm,

    From the above logs, I see that you have 3 GB getting reflected onto the u-boot logs.

    In the SBL, the configuration is basically regarding the DDR registers based on the number of instances. The size of the DDR is retrieved from either u-boot or linux.

    The only place where DDR configuration happens in SBL is in {PDK_PATH}/packages/ti/boot/sbl/board/k3/sbl_main.c in the API Board_init(BOARD_INIT_DDR)


    Regarding splitting of 2 DDR memory bank (i.e. lower 2GB and rest on the higher address) for 1GB on DDRSS0 and 2GB on DDRSS1 needs to be confirmed with the DDR expert.

    I'm currently checking this internally with the DDR expert on how this can be mapped.

    Regards,

    Nikhil

  • 0 in reply to Nikhil Dasan
    TI__Mastermind 34400 points

    Hi,

    From a DDR perspective, you need to setup the DDR and MSMC registers to correspond to the desired hardware configuration. You can use the register configuration tool to help configure these registers. https://www.ti.com/lit/pdf/spracu8 

    If you are using a single rank LPDDR4 on one DDRSS and a dual rank LPDDR4 on the other, than we will have to make one additional modification to the register configuration tool output, as there currently is a limitation with v0.10.0 of the tool that prevents initialization from occurring correctly when the LPDDR4 memories have different number of ranks.

    In addition to the register settings, you need to modify the u-boot source files to define the available memory at the lower and higher order memory regions. This is discussed in section 3.1.2 in the link provided above.

    In the "dram_init_banksize" function, the two regions do not correspond to DDRSS0 and DDRSS1. Instead, they just refer to two different memory regions of the TI Processor where the DDR memory gets mapped to. From a hardware perspective, there is no control over which subset of the address space gets mapped to the DDR memory, and the mapping starts from the lower order memory space. Therefore, you must use the entire lower order memory region first. 

    Regards,
    Kevin

  • 0 in reply to Kevin S
    Expert 1970 points

    Hi, Kevin and Nikhil,

    Received, thanks for the reply. We've purchased the memory chips and will get back to you after we've replaced them on the EVM board and tested.

    Regards,

    Tahm

  • 0 in reply to xie jc
    TI__Guru* 81806 points

    Sure Tahm,

    If there are no further queries, closing this thread.

    Regards,

    Nikhil

  • 0 in reply to Nikhil Dasan
    Expert 1970 points

    Hi, NIkhil,

              We have replaced two Samsung DDR modules on the EVM board (a 16Gb DDR on DDRSS0 and an 8Gb DDR on DDRSS1). After configuring the DDR using the DDR register configuration tool and updating the U-Boot device tree and SBL header files, we conducted tests. We found that the EVM board with unmodified DDR chips could successfully boot to the file system login. However, the EVM board with the two replaced Samsung DDR modules could not start. It got stuck during SBL startup at the DDR initialization stage. I enabled SBL DDR DEBUG printing and found that it was getting stuck at the configuration of the BOARD_DDR_FSP_CLKCHNG_REQ_ADDR register, which had a value of 0, causing it to remain stuck in a while loop. Do you have any insights into the cause of this issue?

    Our DDR configure spreadsheet:

    5545.SPRACU8B_Jacinto7_DDRSS_RegConfigTool-原始-开始配置-DDR0-2GB-DDR1-1GB.rar

    DDR data sheet:

    4087.LP4_16Gb_M_200F_10x15_K4F6E3S4HM-TF(H)CL_Rev1.5.pdf

    2844.[Datasheet]LP4_8Gb_D_200F_10x15_K4F8E3S4HD-GFCL_K4F8E3S4HD-GHCL_Rev1.3(1).pdf

    Best Regards,

    Tahm

  • 0 in reply to xie jc
    Expert 1970 points

    Hi, Nikhil,

    Is this issue related to the Frequency Set Point? When I was configuring the registers using the DDR register configuration tool, I couldn't find any information related to the Frequency Set Point in the Samsung DDR manual. As a result, I left the values in the picture below unchanged. I'm not sure if this is causing the problem.

    Regards,

    Tahm

  • 0 in reply to xie jc
    TI__Guru** 100935 points

    Hi Xie,

    Nikhil is out of office due to the TI regional holiday, and will follow-up once he is back in office later this week.

    regards

    Suman

  • 0 in reply to Suman Anna
    Expert 1970 points

    Hi,  Suman, 

    Thanks for your reply.

    regards

    Tahm

  • 0 in reply to Kevin S
    Expert 1970 points
    Kevin S said:
    perspective

    Hi,  Kevin,

    Can you help us check this issue?

    Best Regards,

    Tahm

  • 0 in reply to xie jc
    Expert 1970 points

    Hi, Nikil and Suman,

    I change  the "Chip Selects / Ranks" from 2 to 1, now the startup looks normal, and can log into the file system.

    but we don't know why, according to the Samsung DDR manual(attached aboved), the chip selects pin should be 2 .

    Regards,

    Tahm

  • 0 in reply to xie jc
    TI__Mastermind 34400 points

    Hi,

    On the IOControl tab, section B ("DRAM IO Configuration"), can you make sure that F0 ODT is enabled and matching the ODT of F1 / F2?

    Regards,
    Kevin

  • 0 in reply to Kevin S
    Expert 1970 points

    Hi, Kevin,

         The ODT config was shown below:

    Regards,

    Tahm

  • 0 in reply to xie jc
    TI__Mastermind 34400 points

    Hi Tahm,

    Thanks, can you please try enabling the CA / DQ ODT for Frequency Set 0?

    Regards,
    Kevin

  • 0 in reply to Kevin S
    Expert 1970 points

    Hi, Kevin, 

    I change the CA DQ ODT to the value as shown below:

    SPRACU8B_Jacinto7_DDRSS_RegConfigTool-cyh-DDR0-2GB-DDR1-1GB-20231101-test.rar

    but the SBL stuck at initlialzing DDR...

    Regards,

    Tahm

  • 0 in reply to xie jc
    TI__Mastermind 34400 points

    Hi Tahm,

    I apologize for the delay - is help still needed here?

    I see that you changed the F0 ODT to RZQ/1; however, I think this needs to be set to match the F1 / F2 setting (CA ODT = RZQ / 3 , and DQ ODT = RZQ/6).

    If still facing issues, can you please give that suggestion a try?

    Regards,
    Kevin

  • 0 in reply to Kevin S
    Expert 1970 points

    Hi, Kevin,

    Thanks for your reply. I change below config:

    I change chipselects/Rank from 2 to 1, it works now.  do you think what i have changed is ok?

    Regards,

    Tahm