AM625: Possible PLL Subsystem TRM Typo

In the TRM (SPRUIV7A – MAY 2022 – REVISED NOVEMBER 2022), I think that there is a footnote to a PLL register table that is incorrect. It currently states:

(1) n = 0 for MCU domain and n = 0 - 2, 8, 12, and 14 for MAIN domain

I believe it should state:

(1) n = 0 for MCU domain and n = 0 - 2, 8, 12, 15, 16, and 17 for MAIN domain

Thanks,

Stuart