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Original question:
Hi team,
SDK version: 8.5/8.6
Platform: Tda4al
Phy: Marvell 88E1510
Because the platform has two identical PHYs attached (different phy addr), the one in the MCU domain is ready to acquire IP, connect the network cable and power on (CLK:25M->125M).
When debugging phy in the Linux main domain and getting IP with udhcpc, the IP is not available and the static IP is not pinged.
When debugging the chip, the RGMII output from phy to clk of Mac, the measured value is 125M,but 50M from Mac to clk, the cable removed is 10M.
Output from MAC to clk of phy as follows:
10M speed:10MHz
100M speed:10MHz
1000M speed:50MHz
I think the problem should be with the output clock "TX_CLK is 10MHz/10MHz/50MHz".
The following figure shows the pin diagram main domain:
ifconfig -a show:
This is what the DTS modifications：
Kernel log is as follows:
Regs of the phy is as follows:
ethtools -S is as follows:
Configure phy from 1000M to 100M speed,enter the following command:
devmem2 0x00683030 w 0x00000068
devmem2 0x00683034 w 0x002AAAAB
devmem2 0x00683080 w 0x00008007
TX output becomes 25M,and the ping is ok!
But speed 10M and 1000M and automatic negotiation mode still can't pinged,now output clk is as follows:
10M speed:25MHz,
100M speed:25MHz,
1000M speed:125MHz.
How to adjust the clk so that the RGMII output the correct clock like in the MCU domain to get the IP?
Could you help check this case? Thanks.
