AM3358: RTC_PWRONRSTn assert time when not using RTC

Hello Tony Tang, 

Thank you for the query.

I need more details on the implementation including how the RC connection to the reset.

The diagram you are showing is 

Figure 6-5. Power-Supply Sequencing With Internal RTC LDO Disabled

Do you have external LDO supplying the RTC?

Regards,

Sreenivasa

Sreenivasa,

#1. RC delay circuit of RTC reset.

PULL down KALDO_1P8V, enabled internal LDO.

Green is the RTC reset. Yellow is VDDS_RTC.

Hello Tony, 

Thank you for the inputs.

Please refer below thread.

(+) AM3352: About the measured voltage from the rise of VDDS_RTC to the rise of RTC_PWRONRSTn - Processors forum - Processors - TI E2E support forums

The reset signal should be below VIL for at least 1ms 

Regards,

Srteenivasa

Sreenivasa,

#1. Even not use the RTC function also need to meet the RTC reset timing? if not meet the timing, what kind of risk may introduce?

#2. If not use the RTC, can the RTC reset keep to low?

Hello Tony, 

Thank you.

Please refer 8.1.4.3.6 Internal RTC LDO of TRM.

Regards,

Sreenivasa

Sreenivasa,

the Section 1 can answer my question #2.

As on customer board, as the LDO is enabled, the circuit use case should follow section 2 use case, but Software did not use RTC, as the RTC reset assert period is not enough, will it impact software operation on RTC or will impact device internal power sequencing?

Hello Tony, 

Based on my understanding, the 1ms reset time is a requirement and i am not sure what would be the effect of not meting the timing. 

I can check internally but not sure if the answer would be different since the thread i lined in the previously message is from the reset expert.

I have a question on the customer configuration and i cant understand clearly with the pictures provided.

What is the customer target configuration?

Please refer below to review the configuration:

Please suggest customer to search RTC_KALDO_ENn in the datasheet and read the notes.

Ex 

CAP_VDD_RTC(4) Supply voltage for the RTC core domain –0.5 1.5 V

(4) This supply is sourced from an internal LDO when RTC_KALDO_ENn is low. If RTC_KALDO_ENn is high, this supply must be sourced from an external power supply.

Regards,

Sreenivasa

Sreenivasa,

It is a Mass Production product, not a new design asking for clarification, as customer strengthened test procedure found this point doesn't meet spec. so ask for help if it has risk.

Hello Tony,

Thank you for the inputs.

I am not sure if i understand your note. Please elaborate.

I will summarize what i have said in the above threads.

The recommendation on the min 1 ms timing is to follow the datasheet. 

RTC_PWRONRSTn should be asserted for at least 1 ms to provide enough time for the internal RTC LDO output to reach a valid level before RTC reset is released. I have also liked the thread from the Reset expert that saya the same.

I do not have any information on the effect of the 1 ms time not being followed on the system performance.

This supply is sourced from an internal LDO when RTC_KALDO_ENn is low. If RTC_KALDO_ENn is high, this supply must be sourced from an external power supply. I do not understand from the provided pictures if the LDO supply is being sourced from outside or not.

I do not see the recommended cap on the supply in the provided picture.

I also mentioned that i will check with the reset expert and update you. Please expect some delay since the expert works out of Dallas.

Pls let me know if you have any additional thoughts or suggestions.

Regards,

Sreenivasa

Sreenivasa,

Kallikuppa Sreenivasa said:

I also mentioned that i will check with the reset expert and update you. Please expect some delay since the expert works out of Dallas.

Thanks for detail elaboration. 

Is there update from reset expert?

Hello Tony,

Thank you for checking.

I have not received any inputs from the expert.

Let me follow-up and update.

Regards,

Sreenivasa

Hello Tony,

Please refer below input i received from the device expert:

The LDO may become stable faster than the 1ms limit on majority of devices, but the limit defined in the datasheet accounts for worst case process corner devices.  Statistically there should not be many of these devices, but there could be a few outliers.  So the risk may be low, but not zero.

Regards,

Sreenivasa