TMS320C6678: Follow up question about EDMA3 Technology

Donjie Billy Hipolito

Part Number: TMS320C6678

EDMA transmission problem: *I have attached the file provided by the customer for easy reference. Your response is highly apprecieated. Thank you.

According to the edma_test.c use case, a block transmission is implemented. If the source address and destination address are both in MSMC, the data transmission result is correct. Configure cmd file, source address in DDR3, while using #pragma DATA_SECTION to set the destination address to MSMC, data transmission error, the code is as follows, perhaps the example understanding is wrong, hope to give advice according to edma_test.c to achieve a block transmission;

The code is as follows:

Attached question from the image. Refer to the example of emda_test.c, set PaRAM as follows, where set ACNT to 256, BCNT to 1, CCNT to 1, using A transfer mode, according to the understanding of the manual，srcBidx=dtsBidx=ACNT,scrCidx=dstCidx=ACNT,But that's not how it's set up in the example.

questions.docx

over 2 years ago

0 Shankari G over 2 years ago

TI__Mastermind 25535 points

Hi,

By any chance, you are able to run the PING PONG test suggested in your previous E2E thread?

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1237332/tms320c6678-inquiry-regarding-the-edma3-technology

Whether it successfully ran on your board?

After changing / hardcoding the values of acnt, bcnt and ccnt, it worked for you?

myParamSetup.srcAddr = (Uint32)srcBuff1;
myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(256,1);
myParamSetup.dstAddr = (Uint32)dstBuff1;
myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(1,1);
myParamSetup.linkBcntrld= CSL_EDMA3_LINKBCNTRLD_MAKE(hParamPong,0);
myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,1);
myParamSetup.cCnt = 1;

Regards

Shankari G

0 Donjie Billy Hipolito over 2 years ago in reply to Shankari G

TI__Prodigy 211 points

I really appreciate the response Shankari. I will relay this to the customer and ask for the result of the ping pong test. Thank you.

0 Shankari G over 2 years ago in reply to Donjie Billy Hipolito

TI__Mastermind 25535 points

Donjie,

Ok.

I think, Opening up multiple threads on the same topic would be difficult to follow and trace the conversations...

Regards

Shankari G.

0 Victor Kazmirenko over 2 years ago

Guru 13202 points

Hello!

Screenshots of the code is something impossible to comprehend, not even tried.

Closer to your question, the major difference between two scenarios is how they are handled by cache. To the best of my knowledge, cache coherency is maintained during EDMA accesses to L2SRAM and MCSRAM, but not maintained in accessed to external memory like DDR3. So the first thing is to make sure cache coherency operations were completed. Again, I cannot read those screenshots, but assuming one uses CPU to write source buffer in DDR3, that operation must be followed by write back operation to force cached data to land to their destination. Then before reading data from external buffers for comparison those those ranges must be invalidated.

Hope this helps.

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TMS320C6678: Follow up question about EDMA3 Technology