AM4378: emulation

Hello Sunitha,

Please confirm: What OS are you developing to run on the AM437x ARM core?

I am not familiar with the Imperas tool. It does not seem to be software published or documented by TI, so we will not be able to answer questions about Imperas specifically.

Regards,

Nick

Hello Nick,

Thank you for responding.

I am using TI SDK am437x-evm-linux-sdk-src-08.02.00.24.tar, default kernel zImage, am437x-sk-evm.dtb files. During Linux kernel bootup, it starts initializing L2 cache controller. Please clarify below.

During L2 cache controller initialization from l2c_write_sec()-->outer_cache.write_sec() --- smc #0 calls are made while writing to Aux register. 

1. Can you please let me know if any register needs to be configured in order to use direct writes to registers by using writel_relaxed() instead of using secure calls(i.e.  _omap_smc1())?

2. If smc #0 calls are made, where are the function handlers defined? Which register needs to be configured for this?

Thanks,

Sunitha

Sunitha a said:

I am trying to emulate AM4378 on a tool called Imperas.

We don't really support what you are trying to do but perhaps we can give you some pointers. Generally speaking, I would recommend running on real HW, rather than trying to emulate an entire device.

Sunitha a said:

1. Can you please let me know if any register needs to be configured in order to use direct writes to registers by using writel_relaxed() instead of using secure calls(i.e.  _omap_smc1())?

What specific device register are you trying to modify?

Sunitha a said:

2. If smc #0 calls are made, where are the function handlers defined? Which register needs to be configured for this?

Those are calls made into ROM Secure Monitor/HAL FW or PPA (Primary Protected Application), and the code itself that is run as a result of those smc calls is not available in source form. However the associated trampoline functions are defined in arch/arm/mach-omap2/omap-smc.S, which gives some insight about the parameters/calling conventions too.

Regards, Andreas

1. During L2 cache controller initialization many registers are updated by kernel. for ex:

0x100 reg1_control 
0x104 reg1_aux_control 
0x108 reg1_tag_ram_control 

Let me see if we can provide some additional pointers here. Will be re-assigning to ROM/PPA expert.

Hello Sunitha,
One reference on SMC call support by ROM
"5.2.11 Services for HLOS Support – API" in AM43xx TRM (www.ti.com/.../spruhl7)
Best,
-Hong

Hello,

I have already reviewed section 5.2.11 from the TRM.

I can modify kernel source to call writel_relaxed() for L2 cache. But is there a way to use direct writes to registers (i.e. writel_relaxed() )instead of using secure calls by configuring any register and without modifying kernel source?