TDA4VM: Issues conecting via Ethernet to EVM when using SBL but not when using SPL

Hi,

Sorry for the delayed response.

We are able to reproduce the issue (We tried on TDA4VL), It is because of CTRLMMR registers are locked by default.
Same issue might be TDAVM as well.

In case of development boot (SBL) or SPL u-boot is unlocking all CTRLMMR blocks so that Interface selection is reflecting in ENET_CTRL register.

In case of optimized boot flow (SBL), where u-boot is not present and SBL loads Linux image no one is unlocking the CTRL MMR blocks so, interface selection to RGMII from ENET_CTRL is not happening as register is locked. (write will not affect the value in register).
This is the reason where you see interface is still RMII even in device tree interface configured as RGMII.

Fix for above:
Unlock the the CTRLMMR registers in SBL or Linux.

Please refer to below changes and add the patch to <PSDK-RTOS>/pdk/packages/ti/boot/sbl/k3/sbl_main.c, where we are unlocking all CTRLMMR from sbl.

 
+#define WKUP_CTRL_MMR0_BASE			0x43000000
+#define MCU_CTRL_MMR0_BASE			0x40f00000
+#define CTRL_MMR0_BASE				0x00100000


+/*
+ * The CTRL_MMR0 memory space is divided into several equally-spaced
+ * partitions, so defining the partition size allows us to determine
+ * register addresses common to those partitions.
+*/
+#define CTRL_MMR0_PARTITION_SIZE		0x4000

+/*
+ * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism
+ * shared register definitions. The same registers are also used for
+ * PADCFG_MMR lock/kick-mechanism.
+*/
+#define CTRLMMR_LOCK_KICK0			0x1008
+#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL		0x68ef3490
+#define CTRLMMR_LOCK_KICK1			0x100c
+#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL		0xd172bc5a


+void CTRL_MMR_unlock(volatile uint32_t baseAddr, uint32_t partition)
+{
+	/* Get the part base address */
+	uint32_t partBaseAddr = baseAddr + (partition * CTRL_MMR0_PARTITION_SIZE);
+
+	/* Unlock the requested partition if locked using two-step sequence */
+	*(volatile uint32_t *)(partBaseAddr + CTRLMMR_LOCK_KICK0) = CTRLMMR_LOCK_KICK0_UNLOCK_VAL;
+	*(volatile uint32_t *)(partBaseAddr + CTRLMMR_LOCK_KICK1) = CTRLMMR_LOCK_KICK1_UNLOCK_VAL;
+}
+
+static void SBL_CTRL_MMR_unlock_all(void)
+{
+	/* Unlock all WKUP_CTRL_MMR0 module registers */
+	CTRL_MMR_unlock(WKUP_CTRL_MMR0_BASE, 0);
+	CTRL_MMR_unlock(WKUP_CTRL_MMR0_BASE, 1);
+	CTRL_MMR_unlock(WKUP_CTRL_MMR0_BASE, 2);
+	CTRL_MMR_unlock(WKUP_CTRL_MMR0_BASE, 3);
+	CTRL_MMR_unlock(WKUP_CTRL_MMR0_BASE, 4);
+	CTRL_MMR_unlock(WKUP_CTRL_MMR0_BASE, 6);
+	CTRL_MMR_unlock(WKUP_CTRL_MMR0_BASE, 7);
+
+	/* Unlock all MCU_CTRL_MMR0 module registers */
+	CTRL_MMR_unlock(MCU_CTRL_MMR0_BASE, 0);
+	CTRL_MMR_unlock(MCU_CTRL_MMR0_BASE, 1);
+	CTRL_MMR_unlock(MCU_CTRL_MMR0_BASE, 2);
+	CTRL_MMR_unlock(MCU_CTRL_MMR0_BASE, 3);
+	CTRL_MMR_unlock(MCU_CTRL_MMR0_BASE, 4);
+
+	/* Unlock all CTRL_MMR0 module registers */
+	CTRL_MMR_unlock(CTRL_MMR0_BASE, 0);
+	CTRL_MMR_unlock(CTRL_MMR0_BASE, 1);
+	CTRL_MMR_unlock(CTRL_MMR0_BASE, 2);
+	CTRL_MMR_unlock(CTRL_MMR0_BASE, 3);
+	CTRL_MMR_unlock(CTRL_MMR0_BASE, 5);
+	 #if defined(SOC_J721S2)
+		CTRL_MMR_unlock(CTRL_MMR0_BASE, 6);
+	#endif
+	CTRL_MMR_unlock(CTRL_MMR0_BASE, 7);
+}


int main()
{
   ......
   
    /* Any SoC specific Init. */
    SBL_SocEarlyInit();

+    /* Unlock control MMR registers */
+    SBL_CTRL_MMR_unlock_all();

    if (SBL_LOG_LEVEL > SBL_LOG_ERR)
    {
        /* Configure UART Tx pinmux. */
        Board_uartTxPinmuxConfig();
    }