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Hello,
When using the internal loopback clock for OSPI/QSPI, is it OK to have a trace/loopback connected to LBCLK0 and DQS0?
For reference, the AM64 Errata specifically states the following under i2303:
The OSPI0_LBCLK0 pin must not have any signal trace connected if the application plans to use the internal pad lookback clocking option.
This is not in the AM62 Errata, nor does the datasheet or TRM specifically state that no signal trace may be connected. Please confirm?
Greetings James,
It's subtle, but "Internal Loopback" and "Internal Pad Loopback" are two different clocking modes. Internal Loopback just uses the internal reference clock to sample data, where as the Internal Pad Loopback option will route a loopback clock directly into DQS/LBCLK to be used as a slightly shifted sampling clock. If there was a trace hooked while using Internal Pad Loopback this may cause signal integrity issues, as while the routing may not go out of the chip it will go through some circuitry that can be potentially affected by a trace on the LBCLK pin.
Sincerely,
Lucas
Hello Lucas,
Thank you for the inputs.
James,
Please refer below section of the datasheet for the connections.
9.2.2 OSPI/QSPI/SPI Board Design and Layout Guidelines
The following section details the PCB routing guidelines that must be observed when connecting OSPI, QSPI, or
SPI devices.
9.2.2.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback
Regards,
Sreenivasa
Thank you both.
Lucan,
To clarify, Figure 9-1 in the datasheet shows no connections for both DQS and LBCLKO for both "Internal PHY Loopback, and Internal Pad Loopback". Based on your comment, is the datasheet incorrect? Or are you describing something more like Figure 9-3? Sorry for the confusion.
Sreenivasa,
Referencing the datasheet, our hardware looks the most similar to Figure 9-2. I understand that Figure 9-1 is the recommended configuration for Internal PHY Loopback, but are you implying that the extra loopback between DQS and LBCLKO affect the Internal PHY Loopback? Is disconnecting the two nets adequate (E.X. removing R1 in Figure 9-1)? Or is any trace length prohibited on the DQS/LBCLKO nets?
Hello James,
Thank you for the inputs.
Sreenivasa,
Referencing the datasheet, our hardware looks the most similar to Figure 9-2. I understand that Figure 9-1 is the recommended configuration for Internal PHY Loopback, but are you implying that the extra loopback between DQS and LBCLKO affect the Internal PHY Loopback? Is disconnecting the two nets adequate (E.X. removing R1 in Figure 9-1)? Or is any trace length prohibited on the DQS/LBCLKO nets?
Looks like you have configured for Figure 9-2. OSPI Connectivity Schematic for External Board Loopback
Here are some thoughts
Please refer below schematics snap shot to configure the LBCLKO
R400 should be placed as close to the LBCLKO pad.
If the OSPI has a DS output, you could connect as shown in the above figure. R421 can be a DNI.
If you do not want to use external loopback DNI R421, R400 and R417. R319 pull down near the SoC OSPI DQS is recommended.
Regards,
Sreenivasa
Thank you,
Some minor clarifications:
If you do not want to use external loopback DNI R421, R400 and R417. R319 pull down near the SoC OSPI DQS is recommended.
In this case, do you mean R396 and not R319?
Hello James,
Thank you for the note and the clarification.
In this case, do you mean R396 and not R319?
This is correct and thank you for helping correct the error.
Regards,
Sreenivasa