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SK-TDA4VM: CSI2/D-PHY on SK vs EVM

Erik Johnson
Intellectual 320 points
Part Number: SK-TDA4VM
Other Parts Discussed in Thread: TDA4VM, TIDA-01413, DRA829,

Hello,

I'm porting some camera capture code from the EVM (Jacinto7 J721E/DRA829/TDA4VM Evaluation Module) to the SK-TDA4VM. Both are connected to the TIDA-01413 (ADAS Fusion board). I'm encountering an issue where our CSI2 driver fails on reading the D-PHY's register DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT56. This register should raise bit 0 (I_CMN_RX_READY) to indicate that "cmn is ready for RX IP" and it does on the EVM, but not on the SK-TDA4VM.

I'm wondering if there is documentation specifically about programming the CSI2/D-PHY subsystem on the J7, specifically the SK-TDA4VM. Also, is the J7 CPU on the SK-TDA4VM necessarily the same w.r.t. the CSI2/D-PHY subsystem as on the EVM? Could you point me to the sample code on this subsystem in the PSDK?

Do the U-Boot binaries from the bootfs (i.e. u-boot.img, tiboot3.bin, tispl.bin, sysfw.itb) perform any initialization of the CSI2/D-PHY that would be specific to PSDK version?

Cheers,

Erik

  • 0
    Intellectual 320 points

    Our driver was missing the initialization code specific to J7 silicon revisions 1.1+ shown in the following:

    void CsirxDrv_dphyrxCoreCommonReady(uint32_t addr)
{
    uint32_t	value, siliconRev;

    siliconRev = CSL_REG32_FEXT((CSL_WKUP_CTRL_MMR0_CFG0_BASE +
                                 CSL_WKUP_CTRL_MMR_CFG0_JTAGID),
                                 WKUP_CTRL_MMR_CFG0_JTAGID_VARIANT);
    if (siliconRev == 0U)
    {
        /* SR 1.0 devices */
        /* Do nothing here*/
    }
    else
    {
        /* SR 1.1 and future silicon revisions */
        /* On J721E PG1.1 and future devices, common module reset will be routed to
           DPHY_RX_MMR_SLV_LANE[23] LANE_RSTB_CMN ,
           this will allow proper reset SW sequence to be executed. */
        /* Release DPHY_RX_MMR_SLV_LANE[23] LANE_RSTB_CMN from reset */
        CSL_REG32_FINS((addr + CSL_DPHY_RX_MMR_SLV + CSL_DPHY_RX_MMR_SLV_LANE),
                        DPHY_RX_MMR_SLV_LANE_LANE_RSTB_CMN,
                        1U);
        /* wait for CMN_READY to be driven to 1 */
        while (0U ==
                (CSL_REG32_FEXT((addr + CSL_DPHY_RX_MMR_SLV +
                                CSL_DPHY_RX_MMR_SLV_LANE),
                                DPHY_RX_MMR_SLV_LANE_CMN_READY)))
        {
            /* wait here till CMN becomes ready */
        }
    }

    /* Wait for CMN to be ready from TBIT56 register */
	value = CSL_REG32_RD(addr + DPHYRX_CMN0_CMN_DIG_TBIT56) & 0x1U;
	while(value != 0x1U)
	{
		value = CSL_REG32_RD(addr + DPHYRX_CMN0_CMN_DIG_TBIT56) & 0x1U;
	}
}