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TDA2SX: tda2xx chip, GPIO2_13 can be interrupted on M4, but not on A15

tian ming
Prodigy 40 points
Part Number: TDA2SX

tda2xx chip, GPIO2_13 can be interrupted on M4, but not on A15, the code is the same, only the interrupt number is different, What should I do, or is there an example in A15

Similarly, I can't interrupt using uart in A15.

Best Regards.

  • 0
    TI__Guru 50045 points

    Hi,

    Did you configure CROSSBAR to route interrupt properly to A15?

    Please refer to TRM CH 18.4.6.4 IRQ_CROSSBAR Module Functional Description.

    Regards,
    Stanley

  • 0 in reply to Stanley Liu
    Prodigy 40 points

    Hi,

    Sorry, I can't find that reference you provided.but I tested interrupt in A15 using the following code:

    GPIO:

        UInt32       gpioBase = SOC_GPIO2_BASE;
        UInt8        gpioPin = 13;
        UInt16       cpuIntrNum = 30;
        UInt32       xBarInst = GPIO2_IRQ_1;
        /* set the mux */
        Tda2xxSetPinmuxRegs((UInt32) 14U, (UInt32) CTRL_CORE_PAD_GPMC_A23, BSP_PLATFORM_IOPAD_CFG_DEFAULT);

        /* Set the GPIO Interrupt Type */
        GPIOIntTypeSet((UInt32) gpioBase, (UInt32) gpioPin, (UInt32) GPIO_INT_TYPE_RISE_EDGE);
        /* Set pin direction as input*/
        GPIODirModeSet((UInt32) gpioBase, (UInt32) gpioPin, (UInt32) GPIO_DIR_INPUT);
        /*Clear interrupt*/
        GPIOPinIntDisable((UInt32) gpioBase, (UInt32) GPIO_INT_LINE_1, (UInt32) gpioPin);
        GPIOPinIntClear((UInt32) gpioBase, (UInt32) GPIO_INT_LINE_1, (UInt32) gpioPin);

        /*Enable interrupt*/
        GPIOPinIntEnable((UInt32) gpioBase, (UInt32) GPIO_INT_LINE_1, (UInt32) gpioPin);
        /* Configure the crossbar */
        BspOsal_irqXbarConnectIrq((UInt32) cpuIntrNum, xBarInst);
        /* Configure the Interrupt */
        BspOsal_clearIntr((UInt32) cpuIntrNum);
        BspOsal_registerIntr((UInt32) cpuIntrNum, &BD_GPS_PPS_GpioIsr, NULL);
    UART:
        UInt16  cpuIntrNum;
        UInt32  xBarInst;
        BspOsal_IntrFuncPtr UARTxIsr;

        Vps_printf("tm: UART%u_Init Intr cfg.\n", uartInstance + 1);

        switch (uartInstance)
        {
            case UART2_INST:
                cpuIntrNum = 73;
                xBarInst = UART2_IRQ;
                UARTxIsr = &UART2Isr;
                break;

            case UART3_INST:
                cpuIntrNum = 45;//IPU1_0:45;MUP:74
                xBarInst = UART3_IRQ;
                UARTxIsr = &UART3Isr;
                break;

            default:
                break;
        }

        /* Configure the crossbar */
        BspOsal_irqXbarConnectIrq((UInt32)cpuIntrNum, xBarInst);

        /* Configure the Interrupt */
        BspOsal_clearIntr((UInt32) cpuIntrNum);  
        gUartxHandle = BspOsal_registerIntr((UInt32) cpuIntrNum, UARTxIsr, NULL);
        if( gUartxHandle == NULL)
        {
            Vps_printf("tm:UART3 INTERRUPT Register Failed !!!\n");
            UTILS_assert(0);
        }
    The problem troubled me and prevented me from continuing my work,
     
    Regards.
  • 0 in reply to tian ming
    Prodigy 40 points

    I found the reference,I use RTOS in tda2sx.

  • 0 in reply to tian ming
    TI__Guru 50045 points

    If you take a look at osal.c, you can find BspOsal_irqXbarConnect(). CPU ID is set based on the macro. Please make sure "__ARM_ARCH_7A__" is set in your A15 build.

    void BspOsal_irqXbarConnect(UInt32 xbarInstance,
                            UInt32 intSource)
{
    CSL_XbarIrqCpuId cpuId = CSL_XBAR_IRQ_CPU_ID_IPU1;
    Int32   retVal = STW_EFAIL;

#if defined (__TI_ARM_V7M4__) || defined (BUILD_IPU1_0) || defined (BUILD_IPU1_1)
    cpuId = CSL_XBAR_IRQ_CPU_ID_IPU1;
    retVal = STW_SOK;
#endif
#if defined (BUILD_IPU2_0) || defined (BUILD_IPU2_1)
    /* Overrides core id if its ipu2, __TI_ARM_V7M4__ is defiend for both IPUs */
    cpuId = CSL_XBAR_IRQ_CPU_ID_IPU2;
    retVal = STW_SOK;
#endif
#if defined (BUILD_DSP_1)
    cpuId = CSL_XBAR_IRQ_CPU_ID_DSP1;
    retVal = STW_SOK;
#endif
#if defined (BUILD_DSP_2)
    cpuId = CSL_XBAR_IRQ_CPU_ID_DSP2;
    retVal = STW_SOK;
#endif
#if defined (__ARM_ARCH_7A__)
    cpuId = CSL_XBAR_IRQ_CPU_ID_MPU;
    retVal = STW_SOK;
#endif
#if defined (BUILD_ARP32_1)
    cpuId = CSL_XBAR_IRQ_CPU_ID_EVE1;
    retVal = STW_SOK;
#endif
#if defined (BUILD_ARP32_2)
    cpuId = CSL_XBAR_IRQ_CPU_ID_EVE2;
    retVal = STW_SOK;
#endif
#if defined (BUILD_ARP32_3)
    cpuId = CSL_XBAR_IRQ_CPU_ID_EVE3;
    retVal = STW_SOK;
#endif
#if defined (BUILD_ARP32_4)
    cpuId = CSL_XBAR_IRQ_CPU_ID_EVE4;
    retVal = STW_SOK;
#endif

    if (STW_SOK == retVal)
    {
        CSL_xbarIrqConfigure(cpuId, xbarInstance, (CSL_XbarIrq) intSource);
    }

    return;
}

  • 0 in reply to Stanley Liu
    Prodigy 40 points

    Thanks you for your informations,use  CSL_xbarIrqConfigure()  At the end of BspOsal_irqXbarConnect() . I changed my code use CSL_xbarIrqConfigure() example:

        UInt32       gpioBase = SOC_GPIO2_BASE;
        UInt8        gpioPin = 13;
        UInt16       cpuIntrNum = 17;
        UInt32       xBarInst = GPIO2_IRQ_1;

        Vps_printf("info:  PPS_ConfigIntr begin...\n");

        CSL_xbarIrqConfigure(CSL_XBAR_IRQ_CPU_ID_MPU, 12, CSL_XBAR_GPIO2_IRQ_1);
        //CSL_xbarIrqConfigure(CSL_XBAR_IRQ_CPU_ID_MPU, 25, CSL_XBAR_GPIO2_IRQ_1);// 25 be used by the NDK

        Intc_IntEnable(cpuIntrNum);
        Intc_IntRegister(cpuIntrNum, (IntrFuncPtr) BD_GPS_PPS_GpioIsr, (void *) 0);
        Intc_IntPrioritySet(cpuIntrNum, 1, 0);
        Intc_SystemEnable(cpuIntrNum);

        /* Enable PRCM*/
        PPS_PrcmEnable();
        /*Reset GPIO*/
        GPIOModuleReset(gpioBase);
        /*Enable GPIO*/
        GPIOModuleEnable(gpioBase);
        /*Configure and enable debouncing feature*/
        GPIODebounceTimeConfig(gpioBase, 0xFF);
        GPIODebounceFuncControl(gpioBase, gpioPin, GPIO_DEBOUNCE_FUNC_ENABLE);
        /* set the mux */
        Tda2xxSetPinmuxRegs((UInt32) 14U, (UInt32) CTRL_CORE_PAD_GPMC_A23, BSP_PLATFORM_IOPAD_CFG_DEFAULT);
        /* Set the GPIO Interrupt Type */
        GPIOIntTypeSet((UInt32) gpioBase, (UInt32) gpioPin, (UInt32) GPIO_INT_TYPE_RISE_EDGE);
        /* Set pin direction as input*/
        GPIODirModeSet((UInt32) gpioBase, (UInt32) gpioPin, (UInt32) GPIO_DIR_INPUT);
        /*Clear interrupt*/
        GPIOPinIntDisable((UInt32) gpioBase, (UInt32) GPIO_INT_LINE_1, (UInt32) gpioPin);
        GPIOPinIntClear((UInt32) gpioBase, (UInt32) GPIO_INT_LINE_1, (UInt32) gpioPin);
        /*Enable interrupt*/
        GPIOPinIntEnable((UInt32) gpioBase, (UInt32) GPIO_INT_LINE_1, (UInt32) gpioPin);

        Vps_printf("info: BD_GPS_PPS_ConfigIntr end...\n");
    Run the code in the serial port output information, A15 stop.
    [HOST ] 15.313822 s: ### XDC ASSERT - ERROR CALLBACK START ###
    [HOST ] 15.313822 s:
    [HOST ] 15.313853 s: E_undefined: Hwi undefined, intnum: 49
    [HOST ] 15.313853 s:
    [HOST ] 15.313883 s: ### XDC ASSERT - ERROR CALLBACK END ###
  • 0 in reply to tian ming
    Prodigy 40 points
       befor Bios_Start(), I call code as follow,
     
        Hwi_Params hwiParams;
        Hwi_Handle myHwi;
        Error_Block eb;
        Error_init(&eb);
        Hwi_Params_init(&hwiParams);
        hwiParams.enableInt = FALSE;
        myHwi = Hwi_create(49, (Hwi_FuncPtr)GPS_PPS_GpioIsr, &hwiParams, &eb);
        if (myHwi == NULL)
        {
            Vps_printf("info: GPS_PPS_GpioIsr: Hwi_create error!");
        }
        else
        {
            Hwi_enableInterrupt(49);
        }
    inptu rise edge on the gpio2_13, uart output:

    [HOST  ]     25.204721 s:  ### XDC ASSERT - ERROR CALLBACK START ###

    [HOST  ]     25.204721 s:

    [HOST  ]     25.204752 s: assertion failure: A_badThreadType: Cannot call a C runtime library API from a Hwi or Swi thread.

    [HOST  ]     25.204782 s:

    [HOST  ]     25.204782 s:  ### XDC ASSERT - ERROR CALLBACK END ###

  • 0 in reply to tian ming
    Prodigy 40 points
    inptu rise edge on the gpio2_13, uart output:

    [HOST  ]     25.204721 s:  ### XDC ASSERT - ERROR CALLBACK START ###

    [HOST  ]     25.204721 s:

    [HOST  ]     25.204752 s: assertion failure: A_badThreadType: Cannot call a C runtime library API from a Hwi or Swi thread.

    [HOST  ]     25.204782 s:

    [HOST  ]     25.204782 s:  ### XDC ASSERT - ERROR CALLBACK END ###

    Beacuse i use Vps_printf() in GPS_PPS_GpioIsr()(it's Interrupt service function ) , after delete Vps_printf() , input rise edge on the gpio2_13, A15 breakdown.

    void GPS_PPS_GpioIsr(UArg arg)
    {
      //Vps_printf("info: in GPS_PPS_GpioIsr...\n");
      Hwi_clearInterrupt(17);
      Hwi_enableInterrupt(17);
      BD_GPS_Uart_Get_Time++;  // test
    }
  • 0 in reply to Stanley Liu
    Prodigy 40 points

    Hi,

    Please help me to check out the latest code.

    Regards.

  • 0 in reply to tian ming
    Prodigy 40 points
    void GPS_PPS_GpioIsr(UArg arg)
    {
      GPIOPinIntClear((UInt32) SOC_GPIO2_BASE, (UInt32) GPIO_INT_LINE_1, (UInt32) 13);  
      BD_GPS_Uart_Get_Time++;  // test
    }