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Hi TI Expert,
I have exactly the same goal and problem as in this referred thread: TDA4VM: Confusion about ECC for DDR Subsystem - Processors forum - Processors - TI E2E support forums
Goal: Enabling DDR ECC for checking SEC/DED errors and report them via ESM interrupts.
And there are further doubts from me based on this thread:
I can see three DDR related ECC aggregators in SDL ECC module, and the corresponding ESM interrupts to them:
I can simply enable them from application layer via SDL_ECC_init(). But I these three ECC AGGRs are not for DDR Inline ECC data error events, right?
If so, then what is purpose for those three ECC AGGRs and should I enable them?
For inline ECC for DDR,
I will need to enable the inline ECC also according to 11.5. Enabling TI’s inline ECC for DDR — Processor SDK QNX J721E.
According to the statement " The inline ECC uses ECC Aggregator interrupts to indicate detection of errors." The DDR inline ECC will trigger the above ESM interrupts for notification.
Once the inline ECC of DDR0 is enabled, any SEC/DED for DDR will directly trigger the below two ESM interrupts:
298 DDR0_DDRSS_DRAM_ECC_CORR_ERR_LVL_0
299 DDR0_DDRSS_DRAM_ECC_UNCORR_ERR_LVL_0
No addition configurations are needed once the inline ECC for DDR is enabled, and the inline ECC to ESM path is already set up. Right?
Thank you so much for your patience.
Hi,
But I these three ECC AGGRs are not for DDR Inline ECC data error events, right?
For SDRAM integrity, the MSMC2DDR bridge interrupts are to be used to test inline ECC on the data written to or read from the SDRAM. The ECC aggregators interrupts pertain to control, config and VBUS.
Inline ECC for SDRAM is enabled by programming the bits in the DDR register and not the ECC aggregators. In this case, ECC is stored together with the data, and the separate ECC Aggregator Interrupts are not used.
Regards,
Josiitaa
Hi Josiitaa,
Thanks for your reply. Understood your description and here are the interrupts of DDRSS routing to main domain ESM:
DDR0_DDRSS_DRAM_ECC_CORR_ERR_LVL_0
DDR0_DDRSS_DRAM_ECC_UNCORR_ERR_LVL_0
These two are the SDRAM inline ECC error events and I can enable them by setting DDR registers and enable ESM, It is clear.
DDR0_DDRSS_CONTROLLER_GLOBAL_ERROR_NONFATAL_0
DDR0_DDRSS_CONTROLLER_GLOBAL_ERROR_FATAL_0
DDR0_DDRSS_CFG_ECC_AGGR_CORR_ERR_LVL_0
DDR0_DDRSS_CFG_ECC_AGGR_UNCORR_ERR_LVL_0
DDR0_DDRSS_CTL_ECC_AGGR_CORR_ERR_LVL_0
DDR0_DDRSS_CTL_ECC_AGGR_UNCORR_ERR_LVL_0
DDR0_DDRSS_VBUS_ECC_AGGR_CORR_ERR_LVL_0
DDR0_DDRSS_VBUS_ECC_AGGR_UNCORR_ERR_LVL_0
Can these 8 interrupts can also enable in ESM at the same time, while I have enabled the inline ECC in SDRAM? Do I need any additional steps to enable them?
Hi,
Yes, the other ECC events can also be enabled. They are for interconnect ECC-related events for DDRSS (not inline ECC). You would also enable the associated ECC aggregators.
Regards,
Josiitaa