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AM6442: Boot Procedure of OSPI in xSPI mode

Hideaki Matsumoto
Expert 8570 points
Part Number: AM6442

Hi,

 

My customer is checking the waveform of access to OSPI Flash in xSPI mode, but the customer is having trouble figuring out where and how the sequence, frequency, and SDR/DDR settings are determined, and whether they are as set or if they can be changed.

 

< Question >

 

Regarding the behavior of the OSPI bus in xSPI mode, from the start of Boot until the user settings take effect, could you please tell them how it works and what sequence and frequency are determined ?

 

Also, they would like to change the frequency of the initial startup sequence (especially 8S-8S-8S). How can they do that ?

Or, is it okay to leave it as it is, because calibration is performed in consideration of temperature fluctuations at the time of initialization?

 

 

< Supplementals >

 

Since there are two chips on the OSPI bus on , they are concerned that the frequency of 170MHz at initialization is high.

 

They’re guessing the procedure like below, but they’re not sure.

 

When the boot mode is determined immediately after the power is turned on,

 the OSPI Flash is accessed with 1S-1S-1S (frequency looks over 6MHz) by the RBL ?

read Flash information ?

and access with 8S-8S-8S (because of the Flash that runs at >170MHz, 200MHz max).?

In addition, there is also a frequency set in the device tree, and normal access operates according to that frequency?

 

These are only speculation.

 

 

Thanks and regards,

Hideaki

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Expert 8570 points

    Hi Sreenivasa,,

    Thank you for sharing the information, but their questions have been not yet resolved. Could you please answer the following their questions ?

    1. Regarding the behavior of the OSPI bus in xSPI mode, from the start of Boot until the user settings take effect, could you please tell them how it works and what sequence and frequency are determined ?
    2. Also, they would like to change the frequency of the initial startup sequence (especially 8S-8S-8S). How can they do that ?

     

    They had already read the TRM and some e2e threads which you proposed. They assume that there is a description of the sequence in which 8D-8D-8D is switched from 1S-1S-1S at the initial startup in the section 4.4.1.2.1 xSPI Bootloader Operation in the TRM, but it seems that the actual measured frequencies at this phase are not 50MHz/25MHz as stated in the TRM. They think that 50MHz/25MHz means only indicates the maximum value.

    What settings actually determine these frequencies ?

     

    At the latter half of Boot, it seems that a waveform of about 170MHz is output. After booting, if they type the command “sf probe”, the same frequency is reproduced.

    What settings determine this frequency ?

    This is much faster than they expected, so they need to figure out how to lower the frequency.

    (Because the two chips are on the same bus)

     

    Furthermore, after booting, if they perform R/W access to a normal memory mapped area, the frequency according to the settings by Device Tree will appear.

     

    Thanks and regards,

    Hideaki

  • 0 in reply to Hideaki Matsumoto
    TI__Guru**** 160279 points

    Hello Hideaki, 

    Thank you.

    I am reassigning the thread to the device expert to comment.

    Regards,

    Sreenivasa

  • +1 in reply to Kallikuppa Sreenivasa
    TI__Expert 3905 points

    Greetings Hideaki,

    I will try to address each question step by step:

    Hideaki Matsumoto said:
    Regarding the behavior of the OSPI bus in xSPI mode, from the start of Boot until the user settings take effect, could you please tell them how it works and what sequence and frequency are determined ?

    The TRM section 4.4.1.2.1 xSPI Bootloader Operation details how xSPI boot works. Essentially there are 3 options:

    1. 1S-1S-1S mode at 50MHz. Read opcode is always 0x0B.
    2. 8D-8D-8D mode at 25 MHz. Read opcode can be selected between 0x0B or 0xEE using the respective BOOTMODE signal.
    3. 1S-1S-1S that will read the SFDP table to switch to 8D-8D-8D at 25MHz. Only works on xSPI memories that have the SFDP table.

    Once the ROM has finished, the SBL and user code can further configure OSPI.

    Hideaki Matsumoto said:
    Also, they would like to change the frequency of the initial startup sequence (especially 8S-8S-8S). How can they do that ?

    The ROM has pre-determined options, but the SBL and user code can be modified by the user themselves. The ROM only supports booting the above options (1-3).

    Hideaki Matsumoto said:
    Or, is it okay to leave it as it is, because calibration is performed in consideration of temperature fluctuations at the time of initialization?

    The ROM does not do any PHY tuning or training.

    Hideaki Matsumoto said:
    < Supplementals >

    Besides xSPI boot, there is a SPI boot that operates at ~6 MHz 1S-1S-1S mode. Perhaps they set it to that initially?

    Hideaki Matsumoto said:

    They had already read the TRM and some e2e threads which you proposed. They assume that there is a description of the sequence in which 8D-8D-8D is switched from 1S-1S-1S at the initial startup in the section 4.4.1.2.1 xSPI Bootloader Operation in the TRM, but it seems that the actual measured frequencies at this phase are not 50MHz/25MHz as stated in the TRM. They think that 50MHz/25MHz means only indicates the maximum value.

    What settings actually determine these frequencies ?

    It's possible that in SFDP xSPI boot it starts off in a 6MHz 1S-1S-1S mode to read the SFDP table, but it will then finish accessing with 8D-8D-8D at 25MHz. Table 4-8. xSPI Boot Configuration Fields show the BOOTMODE pin options to configure xSPI boot.

    Hideaki Matsumoto said:

    At the latter half of Boot, it seems that a waveform of about 170MHz is output. After booting, if they type the command “sf probe”, the same frequency is reproduced.

    What settings determine this frequency ?

    This is much faster than they expected, so they need to figure out how to lower the frequency.

    (Because the two chips are on the same bus)

     

    Furthermore, after booting, if they perform R/W access to a normal memory mapped area, the frequency according to the settings by Device Tree will appear.

    Can you clarify when they performed these observations? My understanding is the following:

    ROM Boot (no user input) -> SBL (no user input but can be changed by user)-> user code running on cores (can input commands over a terminal and can be changed by user)

    If they measured right after the ROM completed and before the SBL touched any registers, they should only see either a 50MHz or 25MHz clock when performing accesses to OSPI. If they measured during the ROM they should see nothing higher than 50MHz or 25MHz. If they measure during or after the SBL it depends on what the SBL or user code is doing.

    Sincerely,

    Lucas