Part Number: TDA4VM
Other Parts Discussed in Thread: TDA4VH
We have TDA4VM as a PCIE RC on our board(not evm board), but there is no clock output from the Serdes pins. Please help solve how to get the clock to output correctly.
1. Board schematic
The left side of the image below is TDA4VM, where PCIE_REFCLK1P\PCIE_REFCLK1N is used as the clock output pin to output the clock to the EP node. (No clock signal output for measurement).
2. SDK version
08.06.01(ti-processor-sdk-linux-j7-evm-08_06_01_02-Linux-x86-Install.bin)
3. Used patch information
Refer to the known FAQ, patch changes have been merged into the code, installed into the TF card, restart the load.
The two addresses 0x00109008 and 0x0010900C are read as 0. The values read from the other addresses are the values written by the patch.
But these two values can be written by :devmem2 0x0010900C w 0xD172BC5A.
Used patch for SDK8.x:/cfs-file/__key/communityserver-discussions-components-files/791/pcie_2D00_ref_2D00_clock_2D00_out_5F00_sdk8.diff
4. Select the clock source
According to the default configuration of the device tree, the internal clock source is used.
serdes_wiz0: wiz@5000000 {
compatible = "ti,j721e-wiz-16g";
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
num-lanes = <2>;
#reset-cells = <1>;
ranges = <0x5000000 0x0 0x5000000 0x10000>;
wiz0_pll0_refclk: pll0-refclk {
clocks = <&k3_clks 292 11>, <&cmn_refclk>;
#clock-cells = <0>;
assigned-clocks = <&wiz0_pll0_refclk>;
assigned-clock-parents = <&k3_clks 292 11>;
};
wiz0_pll1_refclk: pll1-refclk {
clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz0_pll1_refclk>;
assigned-clock-parents = <&k3_clks 292 0>;
};
wiz0_refclk_dig: refclk-dig {
clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz0_refclk_dig>;
assigned-clock-parents = <&k3_clks 292 11>;
};
wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
clocks = <&wiz0_refclk_dig>;
#clock-cells = <0>;
};
wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
clocks = <&wiz0_pll1_refclk>;
#clock-cells = <0>;
};
serdes0: serdes@5000000 {
compatible = "ti,sierra-phy-t0";
reg-names = "serdes";
reg = <0x5000000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
resets = <&serdes_wiz0 0>;
reset-names = "sierra_reset";
clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>;
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll0_refclk", "pll1_refclk";
};
};
