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Original question:

TDA4VM: GPIO cannot be controlled on C66x DSP

TDA4VM: C66x DSP memory map limit some part of MAIN Domain Memory Map

Romain Naour
Intellectual 491 points
Part Number: TDA4VM

Hello,

I had the same issue as reported by [1].

The GPIOs cannot be directly accessed on C66x DSP due to the C66x DSP memory map reserved addresses ranges.

I'm porting a C66x DSP firmware from an AM57xx to a TDA4VM and one of the first step is to enable some GPIOs like the USER LED2 on the SK-TDA4VM board.
But even following the GPIO example provided by the PDK, the GPIO doesn't work at all.

Indeed, we have to enable the RAT address translation to map CSL_GPIO0_BASE to CSL_GPIO0_BASE + CSL_C66_COREPAC_RAT_REGION_BASE.

Actually, for the same reason, this is why the RAT region 15 is initialized by Sciclient_init() using c66xRatRegion configuration parameter.
It allows the DSP to access the interrupt router (C66SS0_INTROUTER0_INTR_ROUTER_CFG, 0x0000AC0000 to 0x0000AC0FFF) because
C66SS0_INTROUTER0_INTR_ROUTER_CFG lies in another reserved range 0x00848000 to 0x00DFFFFF in the C66x DSP memory map.
The RAT initialization is done implicitly by the SCICLIENT API without user can notice it without exploring in details the Sciclient_init() implementation.

While the DSP memory map is described on the TRM (Table 2-6), the "side effect" on register access limitation is not really clear.

The RAT shall not be used only for accessing addresses over 32 bits but also for addresses not available for DSP without translation (example : GPIO base address).

Without RAT, the GPIO library use a reserved memory instead of the GPIO registry.
This is really error prone, at least a new example in the TI-PDK would help to understand this limitation on this SoC and why RAT is necessary.

[1] https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1250481/tda4vm-gpio-cannot-be-controlled-on-c66x-dsp

Best regards,
Romain

  • 0
    TI__Mastermind 41733 points

    Hi Romain,

    For clarification, were you able to get GPIO access from C66x working? And this post is more of a request to include a C66x GPIO example using RAT to be included in the SDK?

    If yes to both, I can route this request to the PDK team to see if we can integrate this to the SDK. If you have a code snippet to share, I can also route that to the PDK team.

    Lastly as a disclaimer, the PDK examples were mainly developed for the EVM board instead of the SK-TDA4VM board. Therefore, there is no guarantee that all of the examples under PDK and PSDK RTOS will work as-is on the SK board. For SK-TDA4VM there is an alternate SDK named PROCESSOR-SDK-LINUX-SK-TDA4VM: https://www.ti.com/tool/download/PROCESSOR-SDK-LINUX-SK-TDA4VM/09.00.01.03. We have a FAQ here that briefly talks about the different SDK and supported boards for reference: https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-edgeai/TDA4VM/09_00_01/exports/docs/devices/TDA4VM/linux/faq.html 

    Regards,

    Takuma

  • +1 in reply to Takuma Fujiwara
    Intellectual 491 points

    Hi Takuma,

    Yes, the gpio access from c66x is working.
    This post was to give a feed back because we were puzzled by this issue and we believe it deserve an example.

    In addition to the gpio driver settings, I did the following:

    rtos_main.c:


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    #include <ti/csl/csl_rat.h>
    [...]
    static void taskFxn(void* a0, void* a1)
    {
    CSL_ratRegs *pC66xRatRegs = (CSL_ratRegs *)CSL_C66_COREPAC_C66_RATCFG_BASE;
    CSL_RatTranslationCfgInfo TranslationCfg;
    GPIO_v0_HwAttrs gpio_cfg;
    /* Initialize SCI Client */
    ipc_initSciclient();
    /*
    * CSL_GPIO0_BASE (0x600000) is not part of the C66x DSP memory map.
    * Like for the DSP interrupt router (see Sciclient_init()),
    * we have to remap CSL_GPIO0_BASE with RAT"
    */
    TranslationCfg.sizeInBytes = CSL_GPIO0_SIZE;
    TranslationCfg.baseAddress = CSL_GPIO0_BASE + CSL_C66_COREPAC_RAT_REGION_BASE;
    TranslationCfg.translatedAddress = CSL_GPIO0_BASE;
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    I don't think this is a problem that is board specific, I believe it could be reproduced on any other board using this SoC.

    Best regards,
    Romain

  • +1 in reply to Romain Naour
    TI__Mastermind 41733 points

    Hi Romain,

    Understood, and thank you for the feedback. Yes, the RAT necessity should affect any board using TDA4VM - just board related things such as which pins are pinned out on the board is different, so most likely the examples will only be validated on the EVM and using pins for the EVM if we integrate this into the SDK.

    I will forward this to our PDK team to see if we can integrate this into a future SDK release.

    Regards,

    Takuma