TDA4VM: M.2 socket not enabled in SDK 09.00.01.03

In addition I got this information:

root@j721e-evm:~# cat /sys/kernel/debug/devices_deferred
2900000.pcie platform: supplier 5000000.serdes not ready

root@j721e-evm:~# dmesg | grep serdes
[ 2.252548] cdns-sierra-phy: probe of 5000000.serdes failed with error -22
[ 6.114276] cdns-sierra-phy 5010000.serdes: Timeout waiting for PHY status ready
[ 6.127499] phy phy-5010000.serdes.9: phy poweron failed --> -110
[ 6.296896] cdns-sierra-phy 5020000.serdes: Timeout waiting for PHY status ready
[ 6.339762] phy phy-5020000.serdes.10: phy poweron failed --> -110

Hi,

The assigned engineer is OoO for Thanksgiving holidays, so please expect delay in response.
Apologies for the inconvenience and thank you for your patience.

Regards,
Parth

Hi Victor,

Apologies for the delay in response and thank you for your patience. I just now tried out the default 9.0.1.3 SDK and have not been able to reproduce the M.2 socket issue. I have plugged in a M.2 NVMe SSD card and it gets detected through lspci.

Victor Cheng said:

Does platform '2900000.pcie: deferred probe pending' correspond to the M.2 slot ?

M.2 slot should be 2920000.pcie.

And based on the dmesg logs, it looks like serdes is failing to initialize, and this will cause PCIe to not initialize. Two questions regarding this:

1. Is the board the TI EVM board, and has there been hardware modifications done to the board?
2. In the software, were the patches in this FAQ applied: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1004565/faq-tda4vm-tda4vm-dra829v-routing-pcie-reference-clock-externally.

If using the default TI EVM board, then the default SDK should work, and the patches should not be applied. However, if hardware modifications to select internal refclk has been made, then the patches should be applied - although, in 9.0 the patches might not be needed since I think we have integrated the feature to automatically use internal refclk when needed.

Regards,

Takuma

Hi Takuma,

Thank you for your quick reply after returning from your holiday break. I have not modified the TI EVM which is a J721EXCP01EVM and the SOM is a J721EX. I didn't apply any patches.

Even if I don't have any M.2 plugged-in, I get the same errors. 

May be I have a defective EVM ?

regards,

Victor

Hi Takuma,

I see a wire in the back of the board. Is it the modification you are referring to ? I attached this image:

Another issue I noticed is when I plugged a HDMI cable into the EVM, the boot doesn't complete, the Uboot keeps rebooting and doesn't proceed to the application processor boot. Without any HDMI cable plugged-in, no problem, the boot completes and I can plug the cable afterwards.

Hi Victor,

The hardware modification is different from the hardware mod in the image. The relevant hardware mod would be below:

There are two resistors near the M.2 slot. Please make sure these resistors are connected to R705 and R706, and not rotated to connect R707 and R708. There are additional two resistors that are covered up by the SOM board, R196 and R197, which should also be checked to make sure they are in "clock gen" configuration instead of "soc" configuration in above image.

As for the hardware mod in your image, it looks like a short between EN pin on LM5060 and the ON/OFF switch:

If the board is turning on, then I assume this is fine. Although, if there are these kinds of hardware mods, I assume it is a very old board.

If you have a different, newer common processor board (CPB), then could you try the experiment out with the newer board? For example, the board I am using for testing is PROC079E3D, where E3D is the revision number.

Regards,

Takuma

I may have an old board because my number is PROC079A

Hi Victor,

PROC079A should be one of the newest revision boards. However, since the board does seem to have some changes based on the picture of the wire, can you confirm if the resistors in my previous post is in the correct position?

In parallel, a colleague of mine is also trying out some experiments on his board to see if he can reproduce this issue.

Regards,

Takuma

Hi Takuma,

Please find attached a pic showing resistors R705 and R706. I think they are correct.

For resistors R196 and R197, can you let me know where they are located ?

Hi Victor,

R196 and R197 are located on the CPB board beneath the SOM board.

Regards,

Takuma

Hi Victor,

Unfortunately, I have not been able to recreate the issue on my end. We received the latest board to see if the difference in observed behavior was due to hardware, but default image seems to detect the M.2 key fine.

Could you clarify how the SD card was created? For example, I am following the "1.1.3.5. Create SD Card with Default Images using script" section in this documentation when creating the SD card: https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-jacinto7/09_01_00_06/exports/docs/linux/Overview/Processor_SDK_Linux_create_SD_card.html#create-sd-card-with-default-images-using-script

With the SD card created with this method, I get the following logs:

root@j721e-evm:~# lspci
0000:00:00.0 PCI bridge: Texas Instruments Device b00d
0001:00:00.0 PCI bridge: Texas Instruments Device b00d
0002:00:00.0 PCI bridge: Texas Instruments Device b00d
0002:01:00.0 Non-Volatile memory controller: Phison Electronics Corporation PS5013 E13 NVMe Controller (rev 01)
root@j721e-evm:~# dmesg | grep pci
[    6.036529] j721e-pcie-host 2900000.pcie: host bridge /bus@100000/pcie@2900000 ranges:
[    6.044622] j721e-pcie-host 2900000.pcie:       IO 0x0010001000..0x0010010fff -> 0x0010001000
[    6.054000] j721e-pcie-host 2900000.pcie:      MEM 0x0010011000..0x0017ffffff -> 0x0010011000
[    6.062621] j721e-pcie-host 2900000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[    6.414779] Modules linked in: videobuf2_v4l2 cfbfillrect videobuf2_common v4l2_async syscopyarea pruss ti_am335x_tscadc cfbimgblt sysfillrect ti_k3_dsp_remoteproc(+) videodev pvrsrvkm(O) sysimgblt ti_j721e_ufs fb_sys_fops virtio_rpmsg_bus cfbcopyarea mc sa2ul rpmsg_ns cdns3_ti cdns_dphy_rx ti_k3_common snd_soc_davinci_mcasp snd_soc_ti_udma snd_soc_ti_edma pci_j721e_host(+) snd_soc_ti_sdma pci_j721e pcie_cadence_host pcie_cadence snd_soc_pcm3168a_i2c m_can_platform m_can snd_soc_pcm3168a can_dev ina2xx optee_rng rng_core rti_wdt cryptodev(O) fuse drm drm_panel_orientation_quirks ipv6
[    7.291828] j721e-pcie-host 2900000.pcie: PCI host bridge to bus 0000:00
[    7.305369] pci_bus 0000:00: root bus resource [bus 00-ff]
[    7.311694] pci_bus 0000:00: root bus resource [io  0x0000-0xffff] (bus address [0x10001000-0x10010fff])
[    7.321798] pci_bus 0000:00: root bus resource [mem 0x10011000-0x17ffffff]
[    7.420119] pci 0000:00:00.0: [104c:b00d] type 01 class 0x060400
[    7.471105] pci_bus 0000:00: 2-byte config write to 0000:00:00.0 offset 0x4 may corrupt adjacent RW1C bits
[    7.545617] pci 0000:00:00.0: supports D1
[    7.550217] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
[    7.557624] pci 0000:00:00.0: reg 0x224: [mem 0x00000000-0x003fffff 64bit]
[    7.565785] pci 0000:00:00.0: VF(n) BAR0 space: [mem 0x00000000-0x00ffffff 64bit] (contains BAR0 for 4 VFs)
[    7.586688] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    7.638010] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
[    7.644894] pci 0000:00:00.0: BAR 7: assigned [mem 0x10400000-0x113fffff 64bit]
[    7.652709] pci 0000:00:00.0: PCI bridge to [bus 01]
[    7.658705] pcieport 0000:00:00.0: PME: Signaling with IRQ 886
[    7.669031] pcieport 0000:00:00.0: AER: enabled with IRQ 886
[    7.682103] j721e-pcie-host 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[    7.718761] j721e-pcie-host 2910000.pcie:       IO 0x0018001000..0x0018010fff -> 0x0018001000
[    7.727668] j721e-pcie-host 2910000.pcie:      MEM 0x0018011000..0x001fffffff -> 0x0018011000
[    7.736295] j721e-pcie-host 2910000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[    8.830872] j721e-pcie-host 2910000.pcie: PCI host bridge to bus 0001:00
[    8.854152] pci_bus 0001:00: root bus resource [bus 00-ff]
[    8.864468] pci_bus 0001:00: root bus resource [io  0x10000-0x1ffff] (bus address [0x18001000-0x18010fff])
[    8.876072] pci_bus 0001:00: root bus resource [mem 0x18011000-0x1fffffff]
[    8.890146] pci 0001:00:00.0: [104c:b00d] type 01 class 0x060400
[    8.897593] pci_bus 0001:00: 2-byte config write to 0001:00:00.0 offset 0x4 may corrupt adjacent RW1C bits
[    8.908030] pci 0001:00:00.0: supports D1
[    8.912324] pci 0001:00:00.0: PME# supported from D0 D1 D3hot
[    8.923116] pci 0001:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    8.931924] pci_bus 0001:01: busn_res: [bus 01-ff] end is updated to 01
[    8.938724] pci 0001:00:00.0: PCI bridge to [bus 01]
[    8.944370] pcieport 0001:00:00.0: PME: Signaling with IRQ 919
[    8.954161] pcieport 0001:00:00.0: AER: enabled with IRQ 919
[    8.990477] j721e-pcie-host 2920000.pcie: host bridge /bus@100000/pcie@2920000 ranges:
[    9.051149] j721e-pcie-host 2920000.pcie:       IO 0x4400001000..0x4400010fff -> 0x0000001000
[    9.087650] j721e-pcie-host 2920000.pcie:      MEM 0x4400011000..0x4407ffffff -> 0x0000011000
[    9.113247] j721e-pcie-host 2920000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[    9.223572] j721e-pcie-host 2920000.pcie: Link up
[    9.228464] j721e-pcie-host 2920000.pcie: PCI host bridge to bus 0002:00
[    9.236148] pci_bus 0002:00: root bus resource [bus 00-ff]
[    9.242286] pci_bus 0002:00: root bus resource [io  0x20000-0x2ffff] (bus address [0x1000-0x10fff])
[    9.252053] pci_bus 0002:00: root bus resource [mem 0x4400011000-0x4407ffffff] (bus address [0x00011000-0x07ffffff])
[    9.263067] pci 0002:00:00.0: [104c:b00d] type 01 class 0x060400
[    9.269176] pci_bus 0002:00: 2-byte config write to 0002:00:00.0 offset 0x4 may corrupt adjacent RW1C bits
[    9.278937] pci 0002:00:00.0: supports D1
[    9.282961] pci 0002:00:00.0: PME# supported from D0 D1 D3hot
[    9.291824] pci 0002:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    9.300034] pci 0002:01:00.0: [1987:5013] type 00 class 0x010802
[    9.306731] pci 0002:01:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit]
[    9.313951] pci 0002:01:00.0: 15.752 Gb/s available PCIe bandwidth, limited by 8.0 GT/s PCIe x2 link at 0002:00:00.0 (capable of 31.504 Gb/s with 8.0 GT/s PCIe x4 link)
[   10.447687] pci_bus 0002:01: busn_res: [bus 01-ff] end is updated to 01
[   10.455211] pci 0002:00:00.0: BAR 14: assigned [mem 0x4400100000-0x44001fffff]
[   10.468265] pci 0002:01:00.0: BAR 0: assigned [mem 0x4400100000-0x4400103fff 64bit]
[   10.477698] pci 0002:00:00.0: PCI bridge to [bus 01]
[   10.488263] pci 0002:00:00.0:   bridge window [mem 0x4400100000-0x44001fffff]
[   10.498158] pcieport 0002:00:00.0: enabling device (0000 -> 0002)
[   10.504847] pcieport 0002:00:00.0: PME: Signaling with IRQ 926
[   10.512185] pcieport 0002:00:00.0: AER: enabled with IRQ 926
[   10.706803] nvme nvme0: pci function 0002:01:00.0
root@j721e-evm:~#

In these logs, the most important logs are:

1. From dmesg output: [ 9.223572] j721e-pcie-host 2920000.pcie: Link up
2. From lspci output: 0002:01:00.0 Non-Volatile memory controller: Phison Electronics Corporation PS5013 E13 NVMe Controller (rev 01)

In the logs shared from your end, dmesg says serdes configuration failed before it can get to "Link up". Since hardware should be the same, my suspicion is whether there is a difference in the SD card image.

Regards,

Takuma