66AK2G12:GPMC_CLK is not being output correctly.

Hello Hidekazu

Thank you for the query.

I need additional information on the implementation assuming this is a custom board.

Has customer performed any testing before implementing the board design.

Regards,

Sreenivasa

Hello Hidekazu

FYI, Refer below

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1071334/notice-regarding-processor-sdk-ti-rtos-for-am335x-am437x-omap-l13x-c674x-k2g-devices

Regards,

Sreenivasa

Dear,Sreenivasa

Thank you for your comment.

I rechecked the Pinmux settings and GPMC_CLK is selected. the other pins of GPMC are also set for GPMC.
GPMCFCLKDIVIDER of GPMC_CONFIG1_0 is changed from 0 to 3. The waveform of GPMC_CLK is as shown in the attachment.

GPMC_CLK.pdf

Can you guess the checkpoints from these waveform results?

Best Regards,
Hidekazu

Hello Hidekazu

Thank you.

With the current information, i do not understand the connections. I need details on how is the connection.

We need to understand the connections. Can you isolate the interfaced device clock and measure the clock output of the processor.

Regards,

Sreenivasa

Hi,Sreenivasa

Detailed connection configuration (circuit diagram) and GPMC_CLK measurement with FPGA disconnected will be disclosed as soon as they are available.

Best Regards,
Hidekazu

Hello Hidekazu

Thank you.

Regards,

Sreenivasa

Hi,Sreenivasa

Attached is the circuit diagram and waveform data around GPMC.
I removed R204 and checked the clock waveform, but there was no change in the waveform.

Circuit diagram:8446.GPMC_CLK.pdf
Clock waveform:gpmc_Circuit.pdf

Could you please point out the problem?

Best Regards,
Hidekazu

Hello Hidekazu

Thank you. 

Please verify and follow the schematics review checklist as below

2.7.2 Peripheral Clock Outputs Put series resistors (close to processor) on the output clocks of the following modules: MMC, GPMC, McASP (both clock and frame sync), SPI, and QSPI. The value of the resistor should be determined using simulation of the PCB. Generally, a 22-Ω resistor is a good starting value.

https://www.ti.com/lit/an/sprac54a/sprac54a.pdf

Regards,

Sreenivasa

Hello Hidekazu

I see a 0R connected on the SPI0_CLK of the 66AK2G12ABY100_DSP.

Please review and follow the checklist.

Regards,

Sreenivasa

Hi,Sreenivasa

I have changed the damping resistor to 22 ohms in the indicated area,
but this has not solved the problem.
Attached is the waveform of the gpmc clk.
gpmc_clk(Waveform):

Are there any other items that should be checked?

Best Regards,
Hidekazu

Hi,Sreenivasa

Regarding the waveform (attached), I was concerned about the waveform at the rise.
It rises to 1.5V and then drops to about 200mV.
Is this expected behavior and not a defect?

Best Regards,
Hidekazu

Hello Hidekazu

Thank you.

Does the GPMC clock connect to multiple devices? 

Can you please isolate the GPMC_CLK series resistor and measure the waveform.

Regards,

Sreenivasa

Hello Hidekazu

Thank you.

Hidekazu said:

Regarding the GPMC_CLK not being output correctly, we have confirmed that
the expected clock is being output by setting GPMCFCLKDIVIDER.
(However, the damping resistor needs to be adjusted.)

Good to hear the progress. The series resistor value adjustment could be due to the layout. 

Hidekazu said:

We are currently checking the timing of each GPMC signal.

Ok.

Regards,

Sreenivasa

Hello Hidekazu

Have you been able to continue the testing?

Regards,

Sreenivasa