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AM5726: AM57x DSP_CLOCK_DIVIDER SR2.0 confusion

John Wilkes
Expert 1315 points
Part Number: AM5726

In SPRUHZ6L it states:

NOTE: Only DSP_CLK3 clock is supported on this SoC. Upon boot time, sysboot15 set at '1' selects
a DSP_CLK3 divided clock version for the DSP subsystem logic and bus interfaces. For
SR1.1, sysboot15 must be tied to vdd to select DSP_CLK3, but for SR2.0 it is configurable.
For more information, see Section 18.4.6.1.1.1, Permanent PU/PD disabling (SR 2.0 only) in
Chapter 18, Control Module.

AND also:

15 DSP_CLOCK_DIVIDER SR1.x Only:
Divide factor for DSP clock
0x0: DSP_CLK2 is selected. Not supported on this SoC.
0x1: DSP_CLK3 is selected
SR2.0 Only:
Permanently disables the internal PU/PD resistors on pads
gpmc_a[27:24, 22:19].
0x0: Internal pull-down resistors are enabled
0x1: Internal pull-down resistors are permanently disabled

Does this mean that SYSBOOT15 has no effect on DSP_CLK for SR2.0?

So, for SR2.0, the DSP subsystem clock is NOT divided by 2 or 3 relative to the DSP DPLL output?

  • 0
    TI__Mastermind 46762 points

    SR2.0 hardwires the divide for DSP_CLK to div-3.

    SR1.1 requires sysboot15 to be in the state to select div-3, and div-2 is unsupported.

    Regards,
    Kyle

  • 0 in reply to kcastille
    Expert 1315 points

    Hi Kyle,

    Thanks for your response, it is a bit clearer now. Can I just get you to check the following to ensure my understanding is correct:

    SYS_CLK1 = 20MHz

    CM_CLKSEL_DPLL_DSP = 0x00004B01

    CM_DIV_M2_DPLL_DSP = 0x00000201

    So I think that the DPLL output is 750MHz: 20Mhz x 75/2 / 1

    Does this mean, for SR2.0, that the C66 cores are clocked at 250MHz because of the DSP clock divider?

    And if so, to get the cores to clock at their maximum 750MHz, I have to increase the DPLL output by three?

    Cheers,

    John.

  • +1 in reply to John Wilkes
    TI__Mastermind 46762 points

    John,

    The DSP core will operate at the full div-1 rate.  The div-3 rate only affects the bus interfaces that are outside of the DSP core.  Namely the EDMA + Interconnect + Cache requests to the rest of the system.

    Regards,

    Kyle

  • 0 in reply to kcastille
    Expert 1315 points

    Hi Kyle,

    OK, that is clear now. Thank you very much for your help.

    Cheers,

    John.