I have modified the default GEL file to initialize DDR3 memory and PLL1 and PLL2. When debugging in no boot mode there are no issues. However when booting from SPI NOR Flash, the DSP successfully boots ( this is confirmed by LED blinking code ). Using LED's I have pinpointed the first line in our DSP code that triggers a exit. We have a "configurePCIe()" function in our main_startupTask that fails. Inside the "configurePCIe()" function we run the following code succesfully:
// Raise the PCIE Reset Line BHS
GPIO_write(FPGA_PCIE_RST, GPIO_PIN_VAL_LOW);
cycleDelay(100000);
GPIO_write(FPGA_PCIE_RST, GPIO_PIN_VAL_HIGH);
pcieRet_e retVal;
int32_t deviceNum = 0;
pcieBarCfg_t barCfg;
pcieIbTransCfg_t ibCfg;
uint16_t lock=0;
void *pcieBase;
if ((retVal = Pcie_init (&pcieInitCfg)) != pcie_RET_OK)
{
printf("LLD device configuration failed\n");
exit(1);
}
/* Turn on the PCIe power domain */
if (CSL_PSC_getPowerDomainState (CSL_PSC_PD_PCIE) != PSC_PDSTATE_ON)
{
/* Enable the domain */
CSL_PSC_enablePowerDomain (CSL_PSC_PD_PCIE);
/* Enable MDCTL */
CSL_PSC_setModuleNextState (CSL_PSC_LPSC_PCIE, PSC_MODSTATE_ENABLE);
/* Apply the domain */
CSL_PSC_startStateTransition (CSL_PSC_PD_PCIE);
/* Wait for it to finish */
while (! CSL_PSC_isStateTransitionDone (CSL_PSC_PD_PCIE));
}
else
{
printf("Power domain is already enabled. You probably re-ran without device reset (which is OK)\n");
}
if ((retVal = Pcie_open(deviceNum, &handle)) != pcie_RET_OK)
{
printf("Pcie Open failed (%d)\n", (int)retVal);
exit(1);
}
/* Configure SERDES*/
uint16_t cfg = 0x01C9; /* value based on PCIe userguide
sprugs6d.pdf, 2.3.1
*/
/* Provide PLL reference clock to SERDES inside PCIESS
Program PLL settings and enable PLL from PCIe SERDES.*/
CSL_BootCfgSetPCIEConfigPLL(cfg);
/*Wait for PLL to lock */
cycleDelay(100000);
/* Set the PCIe mode*/
pcieMode_e PcieMode = pcie_RC_MODE;
if ((retVal = Pcie_setInterfaceMode(handle, PcieMode)) != pcie_RET_OK)
{
printf("Set PCIe Mode failed (%d)\n", (int)retVal);
exit(1);
}
/* Wait until the PCIe SERDES PLL locks */
while (!lock)
{
CSL_BootCfgGetPCIEPLLLock(&lock);
}
printf("PLL configured\n");
After this section we attempt to configure application registers for root complex. This fails. Digging deeper, configuring the application registers for root complex fails when attempting to disable link training. To the deepest level I can dig the program fails here:
if ((retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, regs)) != pcie_RET_OK)
{
displayComment("Read CMD STATUS and DEVICE CMD registers failed!\n");
return retVal;
}
I am not sure why it is failing when booting from SPI NOR Flash yet has no issues when debugging in no boot mode. Any help would be much appreciated.
