Other Parts Discussed in Thread: DRA829,
Hi team,
My customer has a question about DDR initialization in SBL.
File name: pdk_jacinto_08_05_00_36\packages\ti\board\src\j721e_evm\board_ddr.c
static void Board_DDRChangeFreqAck(void)
while(regVal == 0x0)
{
regVal = HW_RD_REG32(BOARD_DDR_FSP_CLKCHNG_REQ_ADDR) & 0x80;
BOARD_DEBUG_LOG("Reg Value: %d \n", regVal);
}
In the above function, they can't get out of the while statement.
What could be the potential for this issue?
【Background】
They have revised our printed circuit board (PCB).
On the revised PCB, components such as GPMC are operating, however, LPDDR4 is not functioning due to the aforementioned issue.
In the previous version of the PCB, LPDDR4 was operating normally.
On the revised PCB, there has been almost no change in the circuit design and layout design around LPDDR4.
On the other hand, customer understand that "the above-mentioned while loop is only related to DDRSS0, CTRL_MMR0, and PLL12 within DRA829, and the LPDDR4 circuit design does not particularly influence this program flow".
As a result, they are at investigation of this problem.
They hope we could give some insights to them if possible.
Thank you in advance.
Best regards,
Kenley
