TMDS64EVM: about timer interrupt routing

Hello TI support team.

I am setting a timer on my CR5.
I would like to know why it is possible to generate an interrupt on CA53 just by registering a timer interrupt on CA53.

What registers or APIs should I check to see if interrupt routing is configured correctly?

Best regards,
Kiyomasa Imaizumi.

Hello Tushar Thakur.

Thank you for your reply.

I understand your explanation.

I have a mysterious problem about interrupt.

I generate a timer in CR5 and periodically route interrupts to CA53. However, there are cases where the routed interrupt does not occur when data is received via Ethernet on the CA53 side.
On the other hand, when the timer was generated using CA53, interrupts were generated without any problems.
What exactly is this difference?

The implementation differences are as follows.
・Generate a timer in CR5 and route interrupts to CA53
・Generate a timer with CA53 and generate an interrupt
According to your explanation, there doesn't seem to be any difference between the two.

I would like to resolve the reason why interrupts do not occur at CA53.
Please tell me how to solve it.

Hello Kiyomasa,

Kiyomasa Imaizumi said:

I generate a timer in CR5 and periodically route interrupts to CA53. However, there are cases where the routed interrupt does not occur when data is received via Ethernet on the CA53 side.

Can you please share the sample code of both(R5F and A53) core for the failing case. (i.e. generating interrupt from R5F and routing to A53)?

It would be helpful for faster debug.

Regards,

Tushar

Hello Tushar Thakur

CA53's project uses a third-party TRON-based OS.
Therefore, it is difficult to deliver the project.

I did some research here.
Besides routed interrupts, I have also tried raising other timer interrupts within CA53.
Below is the waveform.

Ch1:routed interrupt at CA53 (priority = 1) 
Ch2:CR5 interrupt
Ch3:CA53 another timer interrupt (priority = 1)

Ch1 should produce the same waveform as Ch2.

However, if a Ch2 trigger (interrupt from CR5) occurs during a Ch3 timer interrupt, no interrupt will occur in CA53.

If the interrupt routed to CA53 has a priority lower than that timer interrupt, it will not be nested and the interrupt itself will not occur.

Are there any cases where interrupts are not nested?
If a routed interrupt occurs during another CA53 interrupt, is it possible that the routed interrupt does not occur?
Please tell me where should I debug ?

Kiyomasa Imaizumi.

Hello Kiyomasa,

Can you please tell what are the interval/period of the Interrupt that occur on Ch1/2/3?

Also can you please confirm as mentioned in earlier reply when generating interrupt from A53 core and routing to R5 everything works fine. For that case also are the interrupt on Ch1 and Ch3 have same priority?

Can you please check after removing the interrupt coming on Ch3, does everything works fine or still A53 doesn't get interrupt?

Regards,

Tushar

Hello Tushar Thakur.

Can you please tell what are the interval/period of the Interrupt that occur on Ch1/2/3?

The interrupt period for Ch1 and Ch2 is 200us.
The interrupt cycle of Ch3 is 250us.

>Also can you please confirm as mentioned in earlier reply when generating interrupt from A53 core and routing to R5 everything works fine.
>For that case also are the interrupt on Ch1 and Ch3 have same priority?
Where should I check to make sure everything is working properly? Is it a register value somewhere?

>Can you please check after removing the interrupt coming on Ch3, does everything works fine or still A53 doesn't get interrupt?
When I remove the Ch3 interrupt, the interrupt routed to CA53 occurs without any problem.

Why do interrupts routed to CA53 disappear?
I would like to understand what is happening with CA53 interrupts.

Best Regards,
Kiyomasa Imaizumi.

Hello Tushar Thakur.

Something mysterious happened.

This is the case when CR5's TIMER2 interrupt is routed to CA53.
If the CR5 interrupt factor is cleared in the CR5 interrupt handler first, the CA53 interrupt may not be received.
However, if I clear the interrupt source at the end of the CR5 interrupt handler, the CA53 interrupt will enter correctly and periodically.

The interrupt factor clear code is as follows.

// CR5 timer interrupt handler
void CR5_TimerP_isr0(void *args)
{
SET_TEST_J17_1(); // GPIO ON
	// If I put interrupt clear here, interrupt may not occur in CA53.
    TimerP_clearOverflowInt(gTimerBaseAddr[CONFIG_TIMER2]);
    HwiP_clearInt(CONFIG_TIMER2_INT_NUM);

    for(int i = 0; i < 5000; i++){
        ;
    }
	// If I put interrupt clear here, interrupts will occur correctly on CA53 periodically.
//    TimerP_clearOverflowInt(gTimerBaseAddr[CONFIG_TIMER2]);
//    HwiP_clearInt(CONFIG_TIMER2_INT_NUM);


SET_TEST_J17_0(); // GPIO OFF
}

Why does this happen?
Depending on the clearing position of the interrupt factor in CR5, an interrupt may or may not be sent to CA53.

Please tell me the correct way to clear the CR5 and CA53 interrupt sources when using routed interrupts.

Best regards,
Kiyomasa Imaizumi.

Hello Kiyomasa,

Thanks for you response.

Can you please tell us the use case?

I am little confused from the above replies. Can you please provide an overview about the test running on your system?

Can you please tell us how many interrupts are running on A53 or R5F core?

What is the priority, interval and processing time of each interrupt?

Which interrupt are routed on on which core?

Regards,

Tushar