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DRA821U: How to evaluate 10G ethernet

Markus Fister
Prodigy 10 points
Part Number: DRA821U
Other Parts Discussed in Thread: DRA821

Hello support team,

I am looking for an evaluation board for the Jacinto DRA821 processors with a 10G Ethernet port. The only evaluation board I can find is the J721EXCP01EVM which seems to only support 1G Ethernet.

Is there another evaluation board available that has 10G ethernet integrated?

Thanks.

Regards

Markus

  • 0
    TI__Mastermind 22940 points

    Hi,

    Markus Fister said:
    Is there another evaluation board available that has 10G ethernet integrated?

    TI has no EVM support for testing of 10G ethernet.

    Internally we have Bridge connector, through which we are connecting two EVMs back to back in MAC to MAC mode and verifying.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 10 points

    Thanks. So I wonder how you do that bridge connection. Do you use the conector for the quad SGMII Phy for that? It should be possible to reconfigure the serdes lane connected to that connector. That way would it be possible to connect a USXGMII Phy to that port?

    What I don't understand is, that table 12-3870 (SerDes Supported Standards) in the TRM does not list USXGMII as supported. Also it's unclear to me how the CPSW0 would be configured to UXSGMII. Clearly it is supported somehow.

    Best regards

    Markus

  • 0 in reply to Markus Fister
    TI__Mastermind 22940 points

    Hi,

    Markus Fister said:
    Do you use the conector for the quad SGMII Phy for that?

    Will be using the QUAD SGMII connector slot for this, instead of QUAD SGMII will be connecting Bridge connector and the same on other end as well.

    Markus Fister said:
    It should be possible to reconfigure the serdes lane connected to that connector.

    SerDes lane instance can't be changes as it is H/W schematic.
    We can change the functionality of SerDes lane to USXGMII. Also, only Port-1 of CPSW5G supports the USXGMII , the same is configured as SGMII main line in case of QSGMII.

    Markus Fister said:
    What I don't understand is, that table 12-3870 (SerDes Supported Standards) in the TRM does not list USXGMII as supported. Also it's unclear to me how the CPSW0 would be configured to UXSGMII. Clearly it is supported somehow.

    It is supported, internally we have tested.
    TRM need to update.

    Best Regards,
    Sudheer