TMS320VC5509A: Jitter on McBSP output signal

K.Sat

Part Number: TMS320VC5509A

Hi Experts,

Our equipment uses TMS320VC5509A and we are experiencing problems with this equipment.
The problem is that the McBSP output signal has jitter.
As an investigation, I configured the CLKOUT pin to output CPU CLOCK.
As a result, the CPU CLOCK was also experiencing jitter.
The clock input to the X2 pin(approximately 24MHz) is multiplied by the internal clock generator PLL and used as the CPU CLOCK.

As a result of our investigation, we have found the following, but we do not know why this phenomenon occurs.
・Changing the PLL multiplier will change the amount of jitter.(Jitter is larger at x3 than at x4)
・Comparing the idle state and the operating state (where software processing is heavy), the jitter is larger in the operating state.

What are the possible causes of this phenomenon?
We would like to provide specific measurement waveforms on an individual basis.

Additional information
・Power supply voltage is DVDD:3.3V, CVDD:1.6V
・We verified that there is no jitter on the clock input using an oscilloscope and FET probe.

Best regards,

4 months ago

0 Daniel Bermudez 4 months ago

TI__Expert 4370 points

Hello,

As mentioned on the other post, the expert that can help with this is currently OOO, so please allow until next week to get a response. Apologies

Best,

Daniel

0 Ming Wei 4 months ago

TI__Mastermind 45425 points

Hi There,

According to the following diagram, the CPU clock is directly related to the input clock:

The only thing I can think of the CPU clock generated by the DPLL of the DSP Clock Generator. Please configure the CPU clock close to 108Mhz, 144Mhz or 200Mhz.

Best regards,

Ming

0 K.Sat 4 months ago in reply to Ming Wei

Prodigy 20 points

Hi Ming,

Looking at the Data Manual(SPRS205K) and User's Guide(SPRU317K), it says the following.
SPRS205K 5.6.3 Table 5-2 At CVDD=1.2V, 1.35V, 1.6V, X2/CLKIN Cycle time C1=20 ～ 400 ns (=2.5MHz～50MHz)
SPRU317K 3.8 Table 10 Bit11-7 PLLMULT = x2～x31

I thought that the user could freely set the CPU frequency within a specified range.
But does this mean that the jitter performance differs depending on the set frequency?

Best regards,

0 Ming Wei 4 months ago in reply to K.Sat

TI__Mastermind 45425 points

Hi,

That is my guestimatiion. Can you try it out?

Thanks!

Ming

0 K.Sat 4 months ago in reply to Ming Wei

Prodigy 20 points

Hi,
I want to set the McBSP clock frequency to a fixed value, so I cannot set the CPU clock to 108MHz, 144MHz, or 200MHz.
As I wrote at the beginning, when comparing x3 (≒72MHz) and x4 (=96MHz), the jitter of x4 is smaller, but it is not zero.
Between x5(higher than 120MHz) and x4, x5 was smaller.(Closest to 108MHz is x4)
Even with the x5 setting, the jitter is not gone.

Best regards,

0 Ming Wei 4 months ago in reply to K.Sat

TI__Mastermind 45425 points

H K.Sat,

Can you try x6, or even x7 and see whether the jitter is small enough?

Best regards,

Ming

0 K.Sat 4 months ago in reply to Ming Wei

Prodigy 20 points

Hi Ming,

I tried x6, but it had more jitter than x5.(in ordor to operate the equipment, divided by 2 after the PLL)

From this, increasing the multiplier does not necessarily eliminate jitter.

Could you tell me the possible causes and countermeasures, please.

Best regards,

0 Ming Wei 4 months ago in reply to K.Sat

TI__Mastermind 45425 points

Hi K.Sat,

Unfortunately, we do not have the resource to answer the DPLL related questions, because the people who designed the DPLL for C550A are not with TI anymore. Looks like your best option is to use the x5 of the input clock.

Best regards,

Ming

0 Y.F 4 months ago in reply to Ming Wei

Prodigy 10 points

Hi Ming,

This material C5509A is sold WorldWide by Texas Instrument still now.

We strongly belive that it has the responsibility for solving this rejected material problem as Texas Instrument even though no one knows the designed the DPLL for C5509A.

We would like ask you to select the person who has the key executive responsible for this quality issue to solve this problem with us as soon as possible.

Best regards,

0 Ming Wei 4 months ago in reply to Y.F

TI__Mastermind 45425 points

Hi K.Sat and Y.F,

First of all, even the C5509A is still sold worldwide by TI, but the website states clearly that TI does not support new designs for this device anymore:

The other questions we have regarding to this thread are: a) does the jitters only happened in one chip or multiple chips? b) How bigger is the jitter?

Best regards,

Ming

0 K.Sat 4 months ago in reply to Ming Wei

Prodigy 20 points

Hi Ming,

Ans a) Jitter occurs on multiple chips.

Ans b) jitter is not constant, so cannot be measured.

I have a question.

As a device design value, does a slight DPLL jitter occur in an ideal environment?

Best regards,

0 Ming Wei 4 months ago in reply to K.Sat

TI__Mastermind 45425 points

Hi K.Sat,

Thanks a lot for your answers to our questions. It is not an isolated issue for a particular chip, but a general issue with the C5509A in general. Unfortunately, I do not have any document which specifies the jitter range for the DPLL.

As I mentioned before, our support for the legacy devices like C5509A is very limited due to the resources available.

Best regards,

Ming

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TMS320VC5509A: Jitter on McBSP output signal