AM3354: AM3354 Touch Panel issue

Hello Yutaka-san,

What software is running on the AM335x Linux core? Are you still using code that is too old for us to support on the forums?

Regards,

Nick

Dear Nick-san,

Thank you for your reply. 

Yes, The Linux version is Ti's Processor SDK 1.0.0.3.

Based on Chihiro's research, it seems that the latest SDK driver has not been modified.

Best Regards

Yutaka Fukasawa

Hello Yutaka-san,

I know for certain the touch driver changed quite a lot over the years between SDK 1.0.3 and SDK 6.3 (released 4 years ago here: https://www.ti.com/tool/download/PROCESSOR-SDK-LINUX-AM335X/06.03.00.106 ). I am not certain whether the touch driver has had many substantial changes between SDK 6.3 (which is also too old for us to answer design questions on the forums) and the latest SDK 9.1.

I am sending your new thread over to Sreenivasa to comment on whether he thinks that resetting the ADC during runtime would be sufficient to recover from the hung state.

Regards,

Nick

Hello Yutaka-san,

I extracted the recommendations from another thread as below:

The only way to guaranteed it recovers from a hung state is to reset the state machine. The only way to reset the state machine is applying power on reset to the device.

I am internally checking with the device experts on the above workaround.

Regards,

Sreenivasa

Dear Nick-san,  Sreenivasa-san,

Thank you for your reply. 

I really hope the answer to my question is Yes, because we have to apply a workaround to the software and get the product working ASAP.

Best Regards

Yutaka Fukasawa

Hello Yutaka-san,

Thank you.

Yutaka Fukasawa said:

I really hope the answer to my question is Yes, because we have to apply a workaround to the software and get the product working ASAP.

Have you tested the same of you are checking the feasibility.

Pls refer below input from the expert:

We have seen cases where energy from ESD events couples into the ADC from the attached touch panel and causes the ADC state machine to lock-up, such that the only way to recover the ADC is asserting the device cold reset input.

Regards,

Sreenivasa

Dear Sreenivasa-san,

Thank you for your reply. 

Yes. We are experimenting by adding only [statu2]. No issues have occurred so far.

We also read comments from experts. 

Did the experts say that [status2] is necessary as a workaround, but [status1] is unnecessary?

Best Regards

Yutaka Fukasawa

Hello Yutaka-san,

Thank you.

Kallikuppa Sreenivasa said:

Pls refer below input from the expert:

We have seen cases where energy from ESD events couples into the ADC from the attached touch panel and causes the ADC state machine to lock-up, such that the only way to recover the ADC is asserting the device cold reset input.

This is the input i received.

Yutaka Fukasawa said:

[status2]

We are experimenting with a different workaround.

We plan to reset the ADC based on document 12.3.5 below.

AM335x and AMIC110 Sitara Processors Technical Reference Manual (Rev. Q) (ti.com)

12.3.5 Interrupts

Can you please summarize what is the issue you are seeing and how you are recovering using 12.3.5 for me to check with the expertt.

Regards,

Sreenivasa

Dear Sreenivasa-san,

Thank you for your reply. 

The problem that is occurring is that the ADC value cannot be read. So we recovered by resetting the ADC using the method below in 12.3.5.

Excerpt from document 12.3.5

The FIFO can also generate FIFOx_OVERRUN and FIFOx_UNDERFLOW interrupts. The user can mask these events by programming the IRQENABLE_CLR register. To clear a FIFO underflow or FIFO overrun interrupt, the user should write a ‘1’ to the status bit in the IRQSTS register. The TSC_ADC_SS does not recover from these conditions automatically. Therefore, the software will need to disable and then again enable the TSC_ADC_SS. Before the user can turn the module back on, the user must read the ADCSTAT register to check if the status of the ADC FSM is idle and the current step is the idle step.

Best Regards

Yutaka Fukasawa

Hello Yutaka-san,

Thank you for the inputs.

I have shared the inputs with the device expert to get his opinion.

I will update you once i hear back from the expert.

Regards,

Sreenivasa

Dear Sreenivasa-san,

Did you receive a reply from the experts?

I would like to receive an answer as soon as possible.

Best Regards

Yutaka Fukasawa

Hello Yutaka-san,

Thank you for following.

I am following-up and will update when i hear back.

Regards,

Sreenivasa

Hello Sreenivasa-san,

How is the status of follow-up?

Due to the problems occurring in the market, we are hoping for an early update.

Thanks

Best Regards

Masahiro Kobayashi

Hello Yutaka-san,

Thank you for following.

I will following-up and will update you.

Regards,

Sreenivasa

Dear Sreenivasa-san,

The inquiry from two days ago was followed up by the distributor TED Kobayashi-san.

We are going on a long holiday so I won't be able to follow you. very sorry. (4/26～5/6)

Could you please give me a final answer by May 7th?

Best Regards

Yutaka Fukasawa

Hello Yutaka-san,

Thank you for the note.

Yutaka Fukasawa said:

We are going on a long holiday so I won't be able to follow you. very sorry. (4/26～5/6)

Noted.

Yutaka Fukasawa said:

Could you please give me a final answer by May 7th?

Let me follow-up with the team.

Regards,

Sreenivasa

Dear Sreenivasa-san,

How is the status of follow-up?

I have not yet received a final answer.

Please let me know if you need any other information.

Best Regards

Yutaka Fukasawa

Hello Yutaka-san,

Thank you for the note.

I have been following with the designer.

I will update you when i hear from the expert or if the expert has additional queries.

Regards,

Sreenivasa

Hello Yutaka-san,

Could you help me confirm if this is the issue you are seeing and need clarification.

If there is anything additional you would want to add please add so that i can discuss with the expert.

The problem that is occurring is that the ADC value cannot be read. So we recovered by resetting the ADC using the method below in 12.3.5.

Excerpt from document 12.3.5

The FIFO can also generate FIFOx_OVERRUN and FIFOx_UNDERFLOW interrupts. The user can mask these events by programming the IRQENABLE_CLR register. To clear a FIFO underflow or FIFO overrun interrupt, the user should write a ‘1’ to the status bit in the IRQSTS register. The TSC_ADC_SS does not recover from these conditions automatically. Therefore, the software will need to disable and then again enable the TSC_ADC_SS. Before the user can turn the module back on, the user must read the ADCSTAT register to check if the status of the ADC FSM is idle and the current step is the idle step.

Regards,

Sreenivasa

Dear Sreenivasa-san,

Thank you for your support.

I may not have understood your message correctly. very sorry.

We hope to receive a yes or no answer to the following questions.

This is the same content as the first thread input.

Questions

If the issue is resolved with [status2] alone, is [status1] unnecessary?

Is [status2] sufficient as a workaround for the issue?

Please refer to the first thread input for the contents of status1]  and  [status2] .

Best Regards

Yutaka Fukasawa

Hello Yutaka-san,
Thank you for the inputs.
I had a chance to discuss with the designer.
The designer feels the issue you are observing is a classic FIFO overflow.
When you see the issue, looks like the FIFO overflow and does not push data until interrupt is cleared. When interrupt is cleared, FIFO is flushed in the state machine.
The expert believes the workaround that has been implemented seems workable to a pretty high level of confidence.
The expert is continuing to review internally and i will update the thread if i have some additional inputs.

Is there a trend where you observe this issue and have you done any analysis to like reading registers to verify if there is FIFO overflow.

Regards,
Sreenivasa

Dear Sreenivasa-san,

Thank you for your reply.

I understand your discussion. Also, I interpreted the following response as an answer to this issue.

"The expert believes the workaround that has been implemented seems workable to a pretty high level of confidence."

I will report this answer to the development team and see if they have any additional comments.

Best Regards

Yutaka Fukasawa

Hello Yutaka-san,
Thank you for the note.

Regards,

Sreenivasa

Dear Sreenivasa-san,

I received additional comments from the customer. Could you please refer to the following?

■Question

Is an IDLE check required when writing StepEnable to the ADC when no overrun occurs?

Best Regards

Yutaka Fukasawa

Hello Yutaka-san,
Thank you

Yutaka Fukasawa said:

■Question

Is an IDLE check required when writing StepEnable to the ADC when no overrun occurs?

I need to check with the expert.

Could you please check if customer would be able to add additional details regarding th query.

Regards,

Sreenivasa

Dear Sreenivasa-san,

Thank you for your reply.

The customer is a software expert and will be able to answer your questions.

Best Regards

Yutaka Fukasawa

Hello Yutaka-san,
Thank you.

Regards,

Sreenivasa