AM625: SI SIMULATION QUERY

Hemal Patel

Part Number: AM625

Hello Team,

We have completed the layout of this our custom ACM board which is an AM6254ATCGGAALW SOC based design. We have considered an 8 layer stackup in our ACM board. We have followed the PROC114E3_BRD EVK board layout reference which has 10 layers so we have matched the trace width and spacing of this PROC114E3_BRD EVK board 10 Layer stackup in our ACM board 8 layer stackup. And we used the DDR routing of this PROC114E3_BRD EVK board in our ACM board.

We have done the SI simulation and we have below results,

1. When we have considered Pin delay/package delay in this IBIS model in SI simulation then the result is failed.

2. When we have not considered Pin delay/package delay in this IBIS model in SI simulation then the result is Passed.

3. We have observed the same things when we run the SI simulation in ref. EVK board PROC114E3_BRD.

So please check the above results and let us know if you observed this kind of failure in SI or faced any issue in EVK board PROC114E3_BRD performance from your end.

And we have followed the routing of this PROC114E3_BRD EVK board in our board so please confirm that it is the right path we are following or is there any challenge.

Please check the attached 8-Layer stackup, Layout pdf and our ACM board SI report. And let us know if you need anything else from our end.

Ref EVK LAyout Board [E3 Revision]:- https://www.ti.com/lit/zip/sprr448

We have used below IBIS model [AM62x IBIS Model (Rev. D)] for SOC AM6254ATCGGAALW.