TDA4VH-Q1: How to use SGMII driver?

Hi,

SGMII Pins are from SerDes not from CPSW.

jin zhu said:

How can I use SGMII1

SGMII1 corresponding to MAC Port-1 of CPSW9G.

Are you using RTOS based EthFw application or Native Linux Driver for this?

If RTOS based EthFw, you need to change the MAC Port Configuration, SerDes configuration, PHY Driver adding to PDK.
Please refer to below E2E for RTOS based SGMII support.
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1236114/tda4vh-q1-configure-sgmii-serdes

If Linux Native Driver, you need to update device tree overlay for CPSW9G with SGMII and configure the SerDes for SGMII.
Please refer to below E2E for Linux based SGMII support.
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1216735/tda4vh-q1-four-sgmii-port-setting-in-linux-native-driver

Best Regards,
Sudheer

According to the above link, the communication between PC and SGMII1 is still being established.

1. The connection diagram and hardware schematic are as follows:

CPSW9G--SERDES1--SGMII1（PIN：AR3/AR2/AU3/AU2）---PHY（RTL9010）----1000m Transfer box---PC

Q1: Is the configuration of SERDES1 and SGMII1 in CPSW9G done in the Linux SDK or in the RTOS SDK? From the link, it can be seen that the final steps are all related to configuring MCU2-0.

Q2：How to set the clock for SERDES1 (SGMII1) and configure SERDES1 (SGMII1)?

Q3: Does SGMII1 correspond to MAC PORT1? Is the corresponding portNum within the software the software's PORT0?

static Board_STATUS Board_ethConfigCpsw9gEnet1(void)
{
Board_STATUS status = BOARD_SOK;
uint8_t portNum;
printf("[dans] Board_ethConfigCpsw9gEnet1--0\n");
/* Configure the CPSW9G ENET1 QSGMII ports */
for(portNum = 0; portNum < BOARD_CPSW9G_PORT_MAX; portNum++)
{
if ( //1U == portNum ||
5U == portNum ||
6U == portNum ||
7U == portNum )
{
/* These ports are ununsed by default ENET1 board configuration */
continue;
}
else if (1U == portNum)
{
status = Board_cpsw9gMacModeConfig(portNum, SGMII);
printf("[dans] Board_ethConfigCpsw9gEnet0--%d\n",portNum);
}
else if (BOARD_CPSW9G_ENET1_QGMII_PORTNUM == portNum)
{
status = Board_cpsw9gMacModeConfig(portNum, SGMII);
printf("[dans] Board_ethConfigCpsw9gEnet1--%d\n",portNum);
}
else
{
status = Board_cpsw9gMacModeConfig(portNum, QSGMII_SUB);
printf("[dans] Board_ethConfigCpsw9gEnet2--%d\n",portNum);
}

if(status != BOARD_SOK)
{
return BOARD_FAIL;
}
}

return status;
}

Q4: How to ping SGMII1 for tda4vh through the PC end?

Q5: Where do eth2 and eth3 in ifconfig of TDA4VH correspond to?

Current practice: After fixing the following, the driver configuration of phy_rtl9010 can be read. PHY 1 is alive for RTL9010.
Log printing:

root@j784s4-evm:~# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500
inet6 fe80::2ab5:e8ff:feda:3266 prefixlen 64 scopeid 0x20<link>
ether 28:b5:e8:da:32:66 txqueuelen 1000 (Ethernet)
RX packets 92 bytes 10571 (10.3 KiB)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 24 bytes 3828 (3.7 KiB)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

eth1: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500
inet6 fe80::a051:b8ff:feb8:ec71 prefixlen 64 scopeid 0x20<link>
ether a2:51:b8:b8:ec:71 txqueuelen 1000 (Ethernet)
RX packets 1397 bytes 102570 (100.1 KiB)
RX errors 0 dropped 1285 overruns 0 frame 0
TX packets 24 bytes 3828 (3.7 KiB)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

eth2: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500
inet6 fe80::7255:51ff:fea8:392c prefixlen 64 scopeid 0x20<link>
ether 70:55:51:a8:39:2c txqueuelen 1000 (Ethernet)
RX packets 0 bytes 0 (0.0 B)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 27 bytes 4318 (4.2 KiB)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

eth3: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500
inet6 fe80::7283:11ff:feb5:586b prefixlen 64 scopeid 0x20<link>
ether 70:83:11:b5:58:6b txqueuelen 1000 (Ethernet)
RX packets 0 bytes 0 (0.0 B)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 25 bytes 4178 (4.0 KiB)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING> mtu 65536
inet 127.0.0.1 netmask 255.0.0.0
inet6 ::1 prefixlen 128 scopeid 0x10<host>
loop txqueuelen 1000 (Local Loopback)
RX packets 92 bytes 7654 (7.4 KiB)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 92 bytes 7654 (7.4 KiB)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

root@j784s4-evm:~# /opt/vision_apps/vision_apps_init.sh
root@j784s4-evm:~# [MCU2_0] 4.655231 s: CIO: Init ... Done !!!
[MCU2_0] 4.655266 s: ### CPU Frequency = 1000000000 Hz
[MCU2_0] 4.655289 s: CPU is running FreeRTOS
[MCU2_0] 4.655307 s: APP: Init ... !!!
[MCU2_0] 4.655340 s: SCICLIENT: Init ... !!!
[MCU2_0] 4.655460 s: SCICLIENT: DMSC FW version [9.1.2--v09.01.02 (Kool Koala)]
[MCU2_0] 4.655488 s: SCICLIENT: DMSC FW revision 0x9
[MCU2_0] 4.655509 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_0] 4.655531 s: SCICLIENT: Init ... Done !!!
[MCU2_0] 4.655550 s: UDMA: Init ... !!!
[MCU2_0] 4.656395 s: UDMA: Init ... Done !!!
[MCU2_0] 4.656429 s: UDMA: Init for CSITX/CSIRX ... !!!
[MCU2_0] 4.656862 s: UDMA: Init for CSITX/CSIRX ... Done !!!
[MCU2_0] 4.656893 s: MEM: Init ... !!!
[MCU2_0] 4.656917 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ bc800000 of size 268435456 bytes !!!
[MCU2_0] 4.656963 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 60000000 of size 262144 bytes !!!
[MCU2_0] 4.657000 s: MEM: Init ... Done !!!
[MCU2_0] 4.657017 s: IPC: Init ... !!!
[MCU2_0] 4.657052 s: IPC: 11 CPUs participating in IPC !!!
[MCU2_0] 4.657090 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_0] 14.892349 s: IPC: HLOS is ready !!!
[MCU2_0] 14.899888 s: IPC: Init ... Done !!!
[MCU2_0] 14.899934 s: APP: Syncing with 10 CPUs ... !!!
[MCU2_0] 15.592535 s: APP: Syncing with 10 CPUs ... Done !!!
[MCU2_0] 15.592566 s: REMOTE_SERVICE: Init ... !!!
[MCU2_0] 15.593373 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_0] 15.593410 s: dans--ETHFW: Init ... !!!
[MCU2_0] 15.593442 s: dans--EthFwTrace_init
[MCU2_0] 15.593474 s: ETHFW: EthFwBoard_init: dans--EthFwBoard_init
[MCU2_0] 15.594340 s: [dans] Board_init
[MCU2_0] 15.594365 s: [dans] Board_sysInit
[MCU2_0] 15.594538 s: [dans] BOARD_INIT_ENETCTRL_CPSW9G
[MCU2_0] 15.594573 s: [dans] Board_ethConfigCpsw9g==2,==0
[MCU2_0] 15.594596 s: [dans] Board_ethConfigCpsw9gEnet1
[MCU2_0] 15.594617 s: [dans] Board_ethConfigCpsw9gEnet1--0
[MCU2_0] 15.594640 s: [dans] Board_cpsw9gMacModeConfig
[MCU2_0] 15.594662 s: [dans] Board_ethConfigCpsw9gEnet1--1
[MCU2_0] 15.594682 s: [dans] Board_cpsw9gMacModeConfig
[MCU2_0] 15.594703 s: [dans] Board_cpsw9gMacModeConfig
[MCU2_0] 15.594725 s: [dans] Board_cpsw9gMacModeConfig
[MCU2_0] 15.594747 s: [dans] Board_cpsw9gMacModeConfig
[MCU2_0] 15.594774 s: ETHFW: EthFwBoard_init: dans--EthFwBoard_init---1
[MCU2_0] 15.594804 s: ETHFW: EthFwBoard_configQenet: dans=EthFwBoard_configQenet
[MCU2_0] 15.700317 s: dans--appUdmaGetObj
[MCU2_0] 15.700348 s: dans--000000000000
[MCU2_0] 15.700374 s: dans--EthApp_initEthFw
[MCU2_0] 15.700428 s: ETHFW: dans--Warning: Using 6 random MAC address(es)
[MCU2_0] 15.700461 s: ETHFW: Warning: Using 6 MAC address(es) from static pool
[MCU2_0] 15.700589 s: ETHFW: dans--CPSW recovery is not enabled
[MCU2_0] 15.700635 s: ETHFW: dans--EthFwMcast_init
[MCU2_0] 15.700664 s: ETHFW: dans--EthFwMcast_getSharedMcastCfg
[MCU2_0] 15.700688 s: ETHFW: dans--Shared multicasts:
[MCU2_0] 15.700718 s: ETHFW: dans-- 01:00:5e:00:00:01
[MCU2_0] 15.700744 s: ETHFW: dans-- 01:00:5e:00:00:fb
[MCU2_0] 15.700771 s: ETHFW: dans-- 01:00:5e:00:00:fc
[MCU2_0] 15.700797 s: ETHFW: dans-- 33:33:00:00:00:01
[MCU2_0] 15.700822 s: ETHFW: dans-- 33:33:ff:1d:92:c2
[MCU2_0] 15.700848 s: ETHFW: dans-- 01:80:c2:00:00:00
[MCU2_0] 15.700873 s: ETHFW: dans-- 01:80:c2:00:00:03
[MCU2_0] 15.700895 s: ETHFW: dans--Reserved multicasts:
[MCU2_0] 15.700924 s: ETHFW: dans-- 01:80:c2:00:00:0e
[MCU2_0] 15.700951 s: ETHFW: dans-- 01:1b:19:00:00:00
[MCU2_0] 15.701072 s: dans---MCM_GET_HANDLE
[MCU2_0] 15.701105 s: dans--EnetMcm: CPSW_9G on MAIN NAVSS
[MCU2_0] 15.705672 s: Cpsw_open: dans=Cpsw_open
[MCU2_0] 15.705706 s:
[MCU2_0] 15.709826 s: Mdio_open: dans=Mdio_open
[MCU2_0] 15.709856 s:
[MCU2_0] 15.711801 s: dans111---PHY 0 is alive
[MCU2_0] 15.711841 s: dans111---PHY 1 is alive
[MCU2_0] 15.711862 s: dans111---PHY 2 is no alive
[MCU2_0] 15.711884 s: dans111---PHY 3 is no alive
[MCU2_0] 15.711906 s: dans111---PHY 4 is no alive
[MCU2_0] 15.711927 s: dans111---PHY 5 is no alive
[MCU2_0] 15.711948 s: dans111---PHY 6 is no alive
[MCU2_0] 15.711970 s: dans111---PHY 7 is no alive
[MCU2_0] 15.711991 s: dans111---PHY 8 is no alive
[MCU2_0] 15.712012 s: dans111---PHY 9 is no alive
[MCU2_0] 15.712034 s: dans111---PHY 10 is no alive
[MCU2_0] 15.712056 s: dans111---PHY 11 is no alive
[MCU2_0] 15.712084 s: dans111---PHY 12 is no alive
[MCU2_0] 15.712106 s: dans111---PHY 13 is no alive
[MCU2_0] 15.712128 s: dans111---PHY 14 is no alive
[MCU2_0] 15.712150 s: dans111---PHY 15 is no alive
[MCU2_0] 15.712171 s: dans111---PHY 16 is no alive
[MCU2_0] 15.712193 s: dans111---PHY 17 is no alive
[MCU2_0] 15.712214 s: dans111---PHY 18 is no alive
[MCU2_0] 15.712236 s: dans111---PHY 19 is no alive
[MCU2_0] 15.712258 s: dans111---PHY 20 is no alive
[MCU2_0] 15.712279 s: dans111---PHY 21 is no alive
[MCU2_0] 15.712301 s: dans111---PHY 22 is no alive
[MCU2_0] 15.712322 s: dans111---PHY 23 is no alive
[MCU2_0] 15.712344 s: dans111---PHY 24 is no alive
[MCU2_0] 15.712366 s: dans111---PHY 25 is no alive
[MCU2_0] 15.712388 s: dans111---PHY 26 is no alive
[MCU2_0] 15.712409 s: dans111---PHY 27 is no alive
[MCU2_0] 15.712431 s: dans111---PHY 28 is no alive
[MCU2_0] 15.712452 s: dans111---PHY 29 is no alive
[MCU2_0] 15.712474 s: dans111---PHY 30 is no alive
[MCU2_0] 15.712500 s: ETHFW: EthFwBoard_setPortCfg: dans=0EthFwBoard_setPortCfg =0
[MCU2_0] 15.712536 s: EnetPhy_initCfg: dans=EnetPhy_initCfg =0
[MCU2_0] 15.712559 s:
[MCU2_0] 15.712576 s: ETHFW: EthFwBoard_findPortCfg: dans=EthFwBoard_findPortCfg
[MCU2_0] 15.712607 s: ETHFW: EthFwBoard_setPortCfg: dans=3EthFwBoard_setPortCfg =1
[MCU2_0] 15.712637 s: ETHFW: EthFwBoard_setPortCfg: dans=2EthFwBoard_setPortCfg =1
[MCU2_0] 15.712675 s: Cpsw_ioctlInternal: dans=ENET_PER_IOCTL_OPEN_PORT_LINK
[MCU2_0] 15.712701 s:
[MCU2_0] 15.712721 s: Cpsw_ioctlInternal: dans=ENET_PER_IOCTL_OPEN_PORT_LINK =1
[MCU2_0] 15.712747 s:
[MCU2_0] 15.712765 s: Cpsw_openPortLink: dans=Cpsw_openPortLink
[MCU2_0] 15.712787 s:
[MCU2_0] 15.712805 s: Cpsw_openPortLink: dans=Cpsw_openPortLink =1
[MCU2_0] 15.712827 s:
[MCU2_0] 15.712862 s: EnetPhyMdioDflt_getPhyMdio: dans=EnetPhyMdioDflt_getPhyMdio
[MCU2_0] 15.712888 s:
[MCU2_0] 15.712909 s: Cpsw_openPortLinkWithPhy: dans=Cpsw_openPortLinkWithPhy =1
[MCU2_0] 15.712935 s:
[MCU2_0] 15.713226 s: EnetPhy_open: dans=EnetPhy_open =1
[MCU2_0] 15.713250 s:
[MCU2_0] 15.713274 s: EnetPhy_open: dans=EnetPhy_open111
[MCU2_0] 15.713295 s:
[MCU2_0] 15.713436 s: EnetPhy_getId: dans=EnetPhy_getId0000 =732 =33
[MCU2_0] 15.713460 s:
[MCU2_0] 15.713487 s: RTL9010_isPhyDevSupported: dans--PHY 1: RTL9010_isPhyDevSupported
[MCU2_0] 15.713514 s:
[MCU2_0] 15.713763 s: RTL9010Bx_Read_SoftConfig: dans=RTL9010Bx_Read_SoftConfig reg0==140=reg1==d=reg2==1c=reg3==cb30
[MCU2_0] 15.713797 s:
[MCU2_0] 15.714059 s: RTL9010Bx_Read_SoftConfig: dans=RTL9010Bx_Read_SoftConfig reg09==800=regA==7000=regD==0=regE==0
[MCU2_0] 15.714098 s:
[MCU2_0] 15.714235 s: RTL9010Bx_Read_SoftConfig: dans=RTL9010Bx_Read_SoftConfig Page0xA60 reg0x10==3337
[MCU2_0] 15.714265 s:
[MCU2_0] 15.714285 s: RTL9010Ax_Initial_Configuration: dans=RTL9010Ax_Initial_Configuration---0
[MCU2_0] 15.714313 s:
[MCU2_0] 15.716559 s: RTL9010Ax_Initial_Configuration: dans=soft-reset000====8100
[MCU2_0] 15.716586 s:
[MCU2_0] 15.716646 s: RTL9010Ax_Initial_Configuration: dans=soft-reset000====8100
[MCU2_0] 15.716673 s:
[MCU2_0] 15.716735 s: RTL9010Ax_Initial_Configuration: dans=soft-reset000====140
[MCU2_0] 15.716760 s:
[MCU2_0] 15.716781 s: RTL9010Bx_Initial_SGMI_Configuration: dans=RTL9010Bx_Initial_SGMI_Configuration---0
[MCU2_0] 15.716812 s:
[MCU2_0] 15.729376 s: RTL9010Bx_Initial_SGMI_Configuration: dans=soft-reset1111====8100
[MCU2_0] 15.729407 s:
[MCU2_0] 15.729461 s: RTL9010Bx_Initial_SGMI_Configuration: dans=soft-reset1111====8100
[MCU2_0] 15.729488 s:
[MCU2_0] 15.729549 s: RTL9010Bx_Initial_SGMI_Configuration: dans=soft-reset1111====140
[MCU2_0] 15.729577 s:
[MCU2_0] 15.729597 s: RTL9010Ax_Initial_Configuration_Check: dans=RTL9010Ax_Initial_Configuration_Check
[MCU2_0] 15.729628 s:
[MCU2_0] 15.731764 s: RTL9010Ax_Initial_with_SGMII_Configuration_Check: dans=RTL9010Ax_Initial_with_SGMII_Configuration_Check
[MCU2_0] 15.731801 s:
[MCU2_0] 15.753911 s: RTL9010_isPhyDevSupported: dans=RTL9010_isPhyDevSupported---end
[MCU2_0] 15.753938 s:
[MCU2_0] 15.753964 s: EnetPhy_bindDriver: PHY 1: OUI:000732 Model:33 Ver:00 <-> 'RTL9010AS' : OK
[MCU2_0] 15.753994 s:
[MCU2_0] 15.754016 s: ETHFW: EthFwBoard_setPortCfg: dans=0EthFwBoard_setPortCfg =1
[MCU2_0] 15.754047 s: EnetPhy_initCfg: dans=EnetPhy_initCfg =0
[MCU2_0] 15.754069 s:
[MCU2_0] 15.754086 s: ETHFW: EthFwBoard_findPortCfg: dans=EthFwBoard_findPortCfg
[MCU2_0] 15.754115 s: ETHFW: EthFwBoard_setPortCfg: dans=3EthFwBoard_setPortCfg =17
[MCU2_0] 15.754145 s: ETHFW: EthFwBoard_setPortCfg: dans=2EthFwBoard_setPortCfg =17
[MCU2_0] 15.754181 s: Cpsw_ioctlInternal: dans=ENET_PER_IOCTL_OPEN_PORT_LINK
[MCU2_0] 15.754206 s:
[MCU2_0] 15.754225 s: Cpsw_ioctlInternal: dans=ENET_PER_IOCTL_OPEN_PORT_LINK =17
[MCU2_0] 15.754251 s:
[MCU2_0] 15.754268 s: Cpsw_openPortLink: dans=Cpsw_openPortLink
[MCU2_0] 15.754290 s:
[MCU2_0] 15.754308 s: Cpsw_openPortLink: dans=Cpsw_openPortLink =17
[MCU2_0] 15.754330 s:
[MCU2_0] 15.754356 s: EnetPhyMdioDflt_getPhyMdio: dans=EnetPhyMdioDflt_getPhyMdio
[MCU2_0] 15.754383 s:
[MCU2_0] 15.754403 s: Cpsw_openPortLinkWithPhy: dans=Cpsw_openPortLinkWithPhy =17
[MCU2_0] 15.754429 s:
[MCU2_0] 15.754699 s: EnetPhy_open: dans=EnetPhy_open =17
[MCU2_0] 15.754721 s:
[MCU2_0] 15.754745 s: ETHFW: EthFwBoard_setPortCfg: dans=0EthFwBoard_setPortCfg =17
[MCU2_0] 15.754777 s: EnetPhy_initCfg: dans=EnetPhy_initCfg =0
[MCU2_0] 15.754798 s:
[MCU2_0] 15.754813 s: ETHFW: EthFwBoard_findPortCfg: dans=EthFwBoard_findPortCfg
[MCU2_0] 15.754843 s: ETHFW: EthFwBoard_setPortCfg: dans=3EthFwBoard_setPortCfg =18
[MCU2_0] 15.754874 s: ETHFW: EthFwBoard_setPortCfg: dans=2EthFwBoard_setPortCfg =18
[MCU2_0] 15.754906 s: Cpsw_ioctlInternal: dans=ENET_PER_IOCTL_OPEN_PORT_LINK
[MCU2_0] 15.754931 s:
[MCU2_0] 15.754949 s: Cpsw_ioctlInternal: dans=ENET_PER_IOCTL_OPEN_PORT_LINK =18
[MCU2_0] 15.754975 s:
[MCU2_0] 15.754991 s: Cpsw_openPortLink: dans=Cpsw_openPortLink
[MCU2_0] 15.755013 s:
[MCU2_0] 15.755030 s: Cpsw_openPortLink: dans=Cpsw_openPortLink =18
[MCU2_0] 15.755053 s:
[MCU2_0] 15.755102 s: EnetPhyMdioDflt_getPhyMdio: dans=EnetPhyMdioDflt_getPhyMdio
[MCU2_0] 15.755133 s:
[MCU2_0] 15.755155 s: Cpsw_openPortLinkWithPhy: dans=Cpsw_openPortLinkWithPhy =18
[MCU2_0] 15.755181 s:
[MCU2_0] 15.755446 s: EnetPhy_open: dans=EnetPhy_open =18
[MCU2_0] 15.755468 s:
[MCU2_0] 15.755493 s: ETHFW: EthFwBoard_setPortCfg: dans=0EthFwBoard_setPortCfg =18
[MCU2_0] 15.755525 s: EnetPhy_initCfg: dans=EnetPhy_initCfg =0
[MCU2_0] 15.755547 s:
[MCU2_0] 15.755562 s: ETHFW: EthFwBoard_findPortCfg: dans=EthFwBoard_findPortCfg
[MCU2_0] 15.755592 s: ETHFW: EthFwBoard_setPortCfg: dans=3EthFwBoard_setPortCfg =19
[MCU2_0] 15.755622 s: ETHFW: EthFwBoard_setPortCfg: dans=2EthFwBoard_setPortCfg =19
[MCU2_0] 15.755654 s: Cpsw_ioctlInternal: dans=ENET_PER_IOCTL_OPEN_PORT_LINK
[MCU2_0] 15.755678 s:
[MCU2_0] 15.755697 s: Cpsw_ioctlInternal: dans=ENET_PER_IOCTL_OPEN_PORT_LINK =19
[MCU2_0] 15.755722 s:
[MCU2_0] 15.755739 s: Cpsw_openPortLink: dans=Cpsw_openPortLink
[MCU2_0] 15.755761 s:
[MCU2_0] 15.755778 s: Cpsw_openPortLink: dans=Cpsw_openPortLink =19
[MCU2_0] 15.755802 s:
[MCU2_0] 15.755825 s: EnetPhyMdioDflt_getPhyMdio: dans=EnetPhyMdioDflt_getPhyMdio
[MCU2_0] 15.755851 s:
[MCU2_0] 15.755872 s: Cpsw_openPortLinkWithPhy: dans=Cpsw_openPortLinkWithPhy =19
[MCU2_0] 15.755897 s:
[MCU2_0] 15.756166 s: EnetPhy_open: dans=EnetPhy_open =19
[MCU2_0] 15.756189 s:
[MCU2_0] 15.759038 s: ETHFW: 0 VLAN entries added in ALE table
[MCU2_0] 15.759198 s:
[MCU2_0] ETHFW Version : 0.04.00
[MCU2_0] 15.759224 s: ETHFW Build Date: Jun 19, 2024
[MCU2_0] 15.759244 s: ETHFW Build Time: 12:31:20
[MCU2_0] 15.759263 s: ETHFW Commit SHA: 0bf6a31c
[MCU2_0] 15.759300 s: ETHFW: Init ... DONE !!!
[MCU2_0] 15.759492 s: unibase-1.1.4-jacinto
[MCU2_0] 15.759522 s: dans--EthApp_lwipMain
[MCU2_0] 15.760001 s: Starting lwIP, dans --local interface IP is 192.168.11.200
[MCU2_0] 15.760482 s: RTOS: semhandle was NULL
[MCU2_0] 15.760550 s: dans---MCM_GET_HANDLE
[MCU2_0] 15.760604 s: Cpsw_ioctlInternal: dans=ENET_PER_IOCTL_ATTACH_CORE
[MCU2_0] 15.760632 s:
[MCU2_0] 15.765716 s: ETHFW: Host MAC address: 70:63:95:77:90:3f
[MCU2_0] 15.766959 s: ETHFW: Enable gPTP on MAC port 3 (tilld3)
[MCU2_0] 15.766994 s: ETHFW: Enable gPTP on MAC port 5 (tilld5)
[MCU2_0] 15.767067 s: ETHFW: TimeSync PTP enabled
[MCU2_0] 15.767099 s: ETHFW: Remove server Init ... !!!
[MCU2_0] 15.767158 s: ETHFW: Virtual port configuration:
[MCU2_0] 15.767602 s: ETHFW: CpswProxyServer: initialization completed (core: mcu2_0)
[MCU2_0] 15.767634 s: ETHFW: Remove server Init ... DONE !!!
[MCU2_0] 15.768464 s: [LWIPIF_LWIP] Enet LLD netif initialized successfully
[MCU2_0] 15.768521 s: Added interface 'ti0', IP is 192.168.11.200
[MCU2_0] 15.768747 s: dans---MCM_GET_HANDLE
[MCU2_0] 15.768796 s: dans---MCM_GET_HANDLE
[MCU2_0] 15.778677 s: dans---MCM_GET_HANDLE
[MCU2_0] 15.779485 s: dans---MCM_GET_HANDLE
[MCU2_0] 15.779581 s: dans---MCM_GET_HANDLE
[MCU2_0] 15.817089 s: FVID2: Init ... !!!
[MCU2_0] 15.817149 s: FVID2: Init ... Done !!!
[MCU2_0] 15.817265 s: DSS: Init ... !!!
[MCU2_0] 15.817285 s: DSS: Display type is eDP !!!
[MCU2_0] 15.817304 s: DSS: M2M Path is enabled !!!
[MCU2_0] 15.817322 s: DSS: SoC init ... !!!
[MCU2_0] 15.817698 s: DSS: SoC init ... Done !!!
[MCU2_0] 15.817721 s: DSS: Board init ... !!!
[MCU2_0] 15.817738 s: DSS: Board init ... Done !!!
[MCU2_0] 15.836749 s: DSS: Init ... Done !!!
[MCU2_0] 15.836801 s: VHWA: VPAC Init ... !!!
[MCU2_0] 15.836905 s: VHWA: LDC Init ... !!!
[MCU2_0] 15.838606 s: VHWA: LDC Init ... Done !!!
[MCU2_0] 15.838645 s: VHWA: MSC Init ... !!!
[MCU2_0] 15.844527 s: VHWA: MSC Init ... Done !!!
[MCU2_0] 15.844562 s: VHWA: NF Init ... !!!
[MCU2_0] 15.845423 s: VHWA: NF Init ... Done !!!
[MCU2_0] 15.845456 s: VHWA: VISS Init ... !!!
[MCU2_0] 15.850913 s: VHWA: VISS Init ... Done !!!
[MCU2_0] 15.850951 s: VHWA: VPAC Init ... Done !!!
[MCU2_0] 15.850984 s: VX_ZONE_INIT:Enabled
[MCU2_0] 15.851006 s: VX_ZONE_ERROR:Enabled
[MCU2_0] 15.851023 s: VX_ZONE_WARNING:Enabled
[MCU2_0] 15.854401 s: VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU2_0] 15.854433 s: APP: OpenVX Target kernel init ... !!!
[MCU2_0] 15.861850 s: APP: Register tivxRegisterFrontCameraTargetIpuKernels to CPU_mcu2_0 !!!
[MCU2_0] 15.861957 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_0] 15.861983 s: CSI2RX: Init ... !!!
[MCU2_0] 15.862518 s: CSI2RX: Init ... Done !!!
[MCU2_0] 15.862549 s: CSI2TX: Init ... !!!
[MCU2_0] 15.862782 s: CSI2TX: Init ... Done !!!
[MCU2_0] 15.862803 s: ISS: Init ... !!!
[MCU2_0] 15.862828 s: IssSensor_Init ... Done !!!
[MCU2_0] 15.862885 s: IttRemoteServer_Init ... Done !!!
[MCU2_0] 15.862906 s: ISS: Init ... Done !!!
[MCU2_0] 15.862926 s: VISS REMOTE SERVICE: Init ... !!!
[MCU2_0] 15.862973 s: VISS REMOTE SERVICE: Init ... Done !!!
[MCU2_0] 15.862994 s: UDMA Copy: Init ... !!!
[MCU2_0] 15.863965 s: UDMA Copy: Init ... Done !!!
[MCU2_0] 15.864035 s: APP: Init ... Done !!!
[MCU2_0] 15.864057 s: APP: Run ... !!!
[MCU2_0] 15.864073 s: IPC: Starting echo test ...
[MCU2_0] 15.865379 s: APP: Run ... Done !!!
[MCU2_0] 15.865411 s: [dans] Board_init
[MCU2_0] 15.872531 s: ****** appMain: Init completed! *****
[MCU2_0] 15.873982 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[.] mcu3_0[P] mcu3_1[.] mcu4_0[.] mcu4_1[.] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.]
[MCU2_0] 15.874066 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[.] mcu4_0[.] mcu4_1[.] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.]
[MCU2_0] 15.874244 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[.] mcu4_1[.] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.]
[MCU2_0] 15.874316 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[.] mcu4_1[P] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.]
[MCU2_0] 15.874384 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.]
[MCU2_0] 15.874450 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[.] c7x_3[.] c7x_4[.]
[MCU2_0] 15.874518 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[.] c7x_4[.]
[MCU2_0] 15.874584 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[.]
[MCU2_0] 15.874651 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P]
[MCU2_0] 15.955090 s: ***** appSPI Enter! flag:1 *****
[MCU2_0] 15.956123 s: EnetPhy_tick: dans=EnetPhy_resetWaitState =1
[MCU2_0] 15.956153 s:
[MCU2_0] 16.062345 s: ETHFW: VIRT_PORT_INFO | C2S | core=0 endpt=1026
[MCU2_0] 16.062389 s: ETHFW: VIRT_PORT_INFO | S2C | switchPortMask=1 macPortMask=10
[MCU2_0] 16.062496 s: ETHFW: ATTACH_EXT | C2S | core=0 endpt=1026 virtPort=0
[MCU2_0] 16.062556 s: dans---MCM_GET_HANDLE
[MCU2_0] 16.062608 s: Cpsw_ioctlInternal: dans=ENET_PER_IOCTL_ATTACH_CORE
[MCU2_0] 16.062635 s:
[MCU2_0] 16.062832 s: ETHFW: ATTACH_EXT | C2S | core=0 endpt=1026 virtPort=4

Can the above log indicate that SGMII1 configuration is completed?

Hi,

jin zhu said:

Q1: Is the configuration of SERDES1 and SGMII1 in CPSW9G done in the Linux SDK or in the RTOS SDK? From the link, it can be seen that the final steps are all related to configuring MCU2-0.

CPSW9G can be used from A72 Linux using Native Linux Driver, In this case CPSW has to configured from device tree along with SerDes1 for SGMII.
In this case data to/from CPSW9G is forwarded to A72 Linux only no other core will not handle data from CPSW9G.

CPSW9G can also be used from MCU2_0 using Ethernet Firmware (Server) and run clients on Other cores (A72, R5F). In this case CPSW9G data patch enabled for clients as well along with Server.
In case of EthFw application you can configure SerDes from MCU2_0. Please refer to TI Default SDK configuring SerDes2 for QSGMII as per TI EVM.
We also have a configuration for SGMII on same SerDes2 in MCU2_0, as you are using SerDes1 change the SGMII configuration in TI SDK to SerDes1 and invoke SGMII configuration from EthFw application.

SerDes2 SGMII configuration in SDK in below API:

jin zhu said:

Q2：How to set the clock for SERDES1 (SGMII1) and configure SERDES1 (SGMII1)?

You have to set SerDes1 clock, In case of MCU2_0 we are setting clocks for SerDes2, please change the SerDes number to SerDes1 from TI SDK.

Change below to 10G1 for SerDes1. Default it was for SerDes2 as per TI EVM.


If in case of Linux SerDes1 node is available in main.dtsi, need to reference this node and configure SerDes1 for SGMII.

jin zhu said:

Q3: Does SGMII1 correspond to MAC PORT1? Is the corresponding portNum within the software the software's PORT0?

Yes, SGMII1 correspond to MAC PORT1. Which is external Port-1.
Software Port0 means Host Port. Port1 will be MAC Port1.

jin zhu said:

Q4: How to ping SGMII1 for tda4vh through the PC end?

Default MAC PORT1 is mapped to A72 Linux client as MAC only Port in Ethernet Firmware.
If you connect DHCP network, eth2/eth3 on A72 gets IP address, You can ping that IP from PC on the same network.

In Native Linux Driver it will be one of Network interface as per configuration.

jin zhu said:

Q5: Where do eth2 and eth3 in ifconfig of TDA4VH correspond to?

eth2 and eth3 are virtual Port configuration of A72 client as your running MCU2_0 with Ethernet Firmware.
One will corresponds to virtual switch interface (from this you can connect to any of switch ports connected network), another one will be virtual MAC Port interface it will acts as MAC Only Port.
From MAC only Port you can communicate to only the Port-1 connected network.

For more details about switch Port and MAC Port, Please refer to Ethernet Firmware User Guide.

jin zhu said:

Can the above log indicate that SGMII1 configuration is completed?

Have you update Ethernet Port configuration as SGMII and PHY details?
Also, is SerDes1 configured for SGMII? and enable clocks for SerDes1?

If everything is configured properly, and connected Ethernet cable to CPSW9G Port-1, you should observer Link Up message from Ethernet Firmware.
Please refer to Ethernet Firmware sample logs with TI EVM from EthFw User Guide.

Best Regards,
Sudheer

Doredla Sudheer Kumar said:

Wh

hi,

Q1:According to your suggestion, after changing the parameter to 10G1, the MCU2-0 process hung up.And eth2 and eth3 no longer exist.

Changecode:

Hi,

jin zhu said:

[MCU2_0] 16.365837 s: ETHFW: EthFwBoard_configQenet: dans=EthFwBoard_configQenet

As mentioned/suggested above, you suppose to use sgmii configuration, not Qsgmii configuration.
QSGMII is for TI EVM. If you are using TI EVM only SerDes2 is supported.

If you are using custom board, you need to make changes as per your board. Ethernet Port configuration, PHY Address, interface mode..etc.


Best Regards,
Sudheer

hi,

If you are using custom board, you need to make changes as per your board. Ethernet Port configuration, PHY Address, interface mode..etc.

I am currently using a customer board,The configuration connection is as follows:

CPSW9G--SERDES1--SGMII1（PIN：AR3/AR2/AU3/AU2）---PHY（RTL9010）----1000m Transfer box---PC

Q1：How to configure SERDES1-- SGMII1 to SGMII mode, which configurations need to be modified, or provide a demo example?

Q2：Ethernet Port configuration,Which configurations need to be modified or provide demo examples?

Q3：PHY Address, interface mode,Which configurations need to be modified or provide demo examples?

Best Regards

Hi,

Please refer to below E2E, where we helped for enabling SGMII.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1236114/tda4vh-q1-configure-sgmii-serdes

Also, refer to Porting Guide for Ethernet Firmware User Guide.

Also, refer to above comments where I have shared some APIs to be used for SGMII and SerDes clock configuration.


Best Regards,
Sudheer

According to the link, configure as follows:

Hi,

From Logs it looks like SerDes PLL is not locked.
SerDes is not configured properly.

Can you please confirm have you configured SerDes1 for SGMII or not?
Please share your changes related to SerDes configuration & SerDes clock configuration.

I have shared the details about what to do for SerDes clock & configuration and shared other E2E reference as well for enabling SerDes for SGMII. Have you refer to above information?


Best Regards,
Sudheer

The relevant configurations are as follows:

static void EthFwBoard_configSerdesBridge(void)
{
Board_initParams_t prms;
Board_STATUS boardStatus;
ETHFWTRACE_ERR(ETHFW_SOK, "dans=EthFwBoard_configSerdesBridge\r\n");
if (gEthFwBoard.serdesAllowed)
{
// Board_getInitParams(&prms);
// prms.enetBoardID = BOARD_ID_ENET2;
// prms.dualEnetCfg = false;
// Board_setInitParams(&prms);

/* Configure SerDes clocks */
EthFwBoard_configTorrentClks();

/* Configure SerDes for SGMII functionality */
boardStatus = Board_serdesCfgSgmii();
ETHFWTRACE_ERR_IF((boardStatus != BOARD_SOK), boardStatus,
"Failed to configure SerDes for SGMII");
EnetAppUtils_assert(boardStatus == BOARD_SOK);

/* Set MAC mode to SGMII */
boardStatus = Board_cpsw9gMacModeConfig(ENET_MACPORT_NORM(ENET_MAC_PORT_1), SGMII);
ETHFWTRACE_ERR_IF((boardStatus != BOARD_SOK), boardStatus,
"Failed to set SoC MAC mode");
EnetAppUtils_assert(boardStatus == BOARD_SOK);
}
}

clk config:
static void EthFwBoard_configTorrentClks(void)
{
uint32_t moduleId;
uint32_t clkId;
uint32_t clkRateHz;

moduleId = TISCI_DEV_SERDES_10G1;
clkId = TISCI_DEV_SERDES_10G1_CORE_REF_CLK;
clkRateHz = 100000000U;
EnetAppUtils_clkRateSet(moduleId, clkId, clkRateHz);

EnetAppUtils_setDeviceState(moduleId, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0U);
}

sgmii and serdes config:

static Board_STATUS Board_CfgSgmii_serdes1(void)
{
CSL_SerdesResult result;
CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;
CSL_SerdesLaneEnableParams serdesLane0EnableParams = {0};
printf("[dans] Board_CfgSgmii_serdes1 start\n");
printf("%s %d \n",__func__,__LINE__);
memset(&serdesLane0EnableParams, 0, sizeof(serdesLane0EnableParams));

/* SGMII Config */
serdesLane0EnableParams.serdesInstance = (CSL_SerdesInstance)CSL_TORRENT_SERDES1;
serdesLane0EnableParams.baseAddr = CSL_WIZ16B8M4CT3_1_WIZ16B8M4CT3_BASE;
serdesLane0EnableParams.refClock = CSL_SERDES_REF_CLOCK_100M;
serdesLane0EnableParams.refClkSrc = CSL_SERDES_REF_CLOCK_INT0;
serdesLane0EnableParams.linkRate = CSL_SERDES_LINK_RATE_1p25G;
serdesLane0EnableParams.numLanes = 0x1;
serdesLane0EnableParams.laneMask = 0x4;
serdesLane0EnableParams.SSC_mode = CSL_SERDES_NO_SSC;
serdesLane0EnableParams.phyType = CSL_SERDES_PHY_TYPE_SGMII;
serdesLane0EnableParams.operatingMode = CSL_SERDES_FUNCTIONAL_MODE;
serdesLane0EnableParams.phyInstanceNum = 0;//BOARD_SERDES_LANE_SELECT_CPSW;
serdesLane0EnableParams.pcieGenType = CSL_SERDES_PCIE_GEN3;

serdesLane0EnableParams.laneCtrlRate[0] = CSL_SERDES_LANE_FULL_RATE;
serdesLane0EnableParams.loopbackMode[0] = CSL_SERDES_LOOPBACK_DISABLED;

serdesLane0EnableParams.laneCtrlRate[1] = CSL_SERDES_LANE_FULL_RATE;
serdesLane0EnableParams.loopbackMode[1] = CSL_SERDES_LOOPBACK_DISABLED;
printf("%s %d \n",__func__,__LINE__);

CSL_serdesPorReset(serdesLane0EnableParams.baseAddr);
printf("%s %d \n",__func__,__LINE__);

/* Select the IP type, IP instance num, Serdes Lane Number */
CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
serdesLane0EnableParams.phyType,
serdesLane0EnableParams.phyInstanceNum,
serdesLane0EnableParams.serdesInstance,
0U);
/* Select the IP type, IP instance num, Serdes Lane Number */
CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
serdesLane0EnableParams.phyType,
serdesLane0EnableParams.phyInstanceNum,
serdesLane0EnableParams.serdesInstance,
1U);
/* Select the IP type, IP instance num, Serdes Lane Number */
CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
serdesLane0EnableParams.phyType,
serdesLane0EnableParams.phyInstanceNum,
serdesLane0EnableParams.serdesInstance,
2U);
/* Select the IP type, IP instance num, Serdes Lane Number */
CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
serdesLane0EnableParams.phyType,
serdesLane0EnableParams.phyInstanceNum,
serdesLane0EnableParams.serdesInstance,
3U);

printf("%s %d \n",__func__,__LINE__);

result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,
serdesLane0EnableParams.baseAddr,
serdesLane0EnableParams.refClock,
serdesLane0EnableParams.refClkSrc,
serdesLane0EnableParams.serdesInstance,
serdesLane0EnableParams.phyType);
printf("%s %d \n",__func__,__LINE__);

if (result != CSL_SERDES_NO_ERR)
{
return BOARD_FAIL;
}
printf("%s %d \n",__func__,__LINE__);

/* Assert PHY reset and disable all lanes */
CSL_serdesDisablePllAndLanes(serdesLane0EnableParams.baseAddr, serdesLane0EnableParams.numLanes, serdesLane0EnableParams.laneMask);
printf("%s %d \n",__func__,__LINE__);

/* Load the Serdes Config File */
result = CSL_serdesEthernetInit(&serdesLane0EnableParams);
/* Return error if input params are invalid */
if (result != CSL_SERDES_NO_ERR)
{
return BOARD_FAIL;
}
printf("%s %d \n",__func__,__LINE__);

/* Common Lane Enable API for lane enable, pll enable etc */
laneRetVal = CSL_serdesLaneEnable(&serdesLane0EnableParams);
if (laneRetVal != 0)
{
return BOARD_FAIL;
}
printf("%s %d \n",__func__,__LINE__);
printf("[dans] Board_CfgSgmii_serdes1 end\n");
return BOARD_SOK;
}

The above is the relevant configuration, please help to check it。

Hi,

jin zhu said:

// /* Unlock MMR write access */

// Board_serdesKickCtrl(0);

jin zhu said:

#if 0

ret = Board_CfgSgmii(boardID);

// Board_serdesKickCtrl(1); /* Lock MMR write access */

#endif

You should not comment Unlock and Lock of MMR registers.

If MMR registers are not unlocked the value writing into MMR registers will not reflect.

The Sequence should be Unlock the MMR  -> Configure the SerDes -> Lock the MMR.

Best Regards,
Sudheer

ok, change after:

Same error log message：

root@j784s4-evm:~# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500
inet6 fe80::2ab5:e8ff:feda:3266 prefixlen 64 scopeid 0x20<link>
ether 28:b5:e8:da:32:66 txqueuelen 1000 (Ethernet)
RX packets 0 bytes 0 (0.0 B)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 19 bytes 2686 (2.6 KiB)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

eth1: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500
inet6 fe80::b8da:41ff:fe16:18d0 prefixlen 64 scopeid 0x20<link>
ether ba:da:41:16:18:d0 txqueuelen 1000 (Ethernet)
RX packets 277 bytes 20340 (19.8 KiB)
RX errors 0 dropped 255 overruns 0 frame 0
TX packets 21 bytes 3090 (3.0 KiB)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING> mtu 65536
inet 127.0.0.1 netmask 255.0.0.0
inet6 ::1 prefixlen 128 scopeid 0x10<host>
loop txqueuelen 1000 (Local Loopback)
RX packets 92 bytes 7654 (7.4 KiB)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 92 bytes 7654 (7.4 KiB)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

root@j784s4-evm:~# /opt/vision_apps/vision_apps_init.sh
root@j784s4-evm:~# [MCU2_0] 4.749329 s: CIO: Init ... Done !!!
[MCU2_0] 4.749365 s: ### CPU Frequency = 1000000000 Hz
[MCU2_0] 4.749391 s: CPU is running FreeRTOS
[MCU2_0] 4.749407 s: APP: Init ... !!!
[MCU2_0] 4.749441 s: SCICLIENT: Init ... !!!
[MCU2_0] 4.749564 s: SCICLIENT: DMSC FW version [9.1.2--v09.01.02 (Kool Koala)]
[MCU2_0] 4.749594 s: SCICLIENT: DMSC FW revision 0x9
[MCU2_0] 4.749613 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_0] 4.749633 s: SCICLIENT: Init ... Done !!!
[MCU2_0] 4.749651 s: UDMA: Init ... !!!
[MCU2_0] 4.750516 s: UDMA: Init ... Done !!!
[MCU2_0] 4.750548 s: UDMA: Init for CSITX/CSIRX ... !!!
[MCU2_0] 4.750972 s: UDMA: Init for CSITX/CSIRX ... Done !!!
[MCU2_0] 4.751001 s: MEM: Init ... !!!
[MCU2_0] 4.751024 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ bc800000 of size 268435456 bytes !!!
[MCU2_0] 4.751065 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 60000000 of size 262144 bytes !!!
[MCU2_0] 4.751099 s: MEM: Init ... Done !!!
[MCU2_0] 4.751115 s: IPC: Init ... !!!
[MCU2_0] 4.751148 s: IPC: 11 CPUs participating in IPC !!!
[MCU2_0] 4.751185 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_0] 15.066119 s: IPC: HLOS is ready !!!
[MCU2_0] 15.073320 s: IPC: Init ... Done !!!
[MCU2_0] 15.073368 s: APP: Syncing with 10 CPUs ... !!!
[MCU2_0] 15.838096 s: APP: Syncing with 10 CPUs ... Done !!!
[MCU2_0] 15.838130 s: REMOTE_SERVICE: Init ... !!!
[MCU2_0] 15.838952 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_0] 15.838996 s: dans--ETHFW: Init ... !!!
[MCU2_0] 15.839029 s: dans--EthFwTrace_init
[MCU2_0] 15.839061 s: ETHFW: EthFwBoard_init: dans--EthFwBoard_init
[MCU2_0] 15.839590 s: [dans] Board_init
[MCU2_0] 15.839614 s: [dans] Board_sysInit
[MCU2_0] 15.839805 s: [dans] BOARD_INIT_ENETCTRL_CPSW9G
[MCU2_0] 15.839841 s: [dans] Board_ethConfigCpsw9g==2,==0
[MCU2_0] 15.839862 s: [dans] Board_ethConfigCpsw9gEnet1
[MCU2_0] 15.839883 s: [dans] Board_ethConfigCpsw9gEnet1--0
[MCU2_0] 15.839913 s: [dans] Board_cpsw9gMacModeConfig==0===3
[MCU2_0] 15.839945 s: [dans] Board_ethConfigCpsw9gEnet1--0
[MCU2_0] 15.839974 s: [dans] Board_cpsw9gMacModeConfig==2===3
[MCU2_0] 15.840005 s: [dans] Board_ethConfigCpsw9gEnet2--2
[MCU2_0] 15.840034 s: [dans] Board_cpsw9gMacModeConfig==3===3
[MCU2_0] 15.840063 s: [dans] Board_ethConfigCpsw9gEnet2--3
[MCU2_0] 15.840092 s: [dans] Board_cpsw9gMacModeConfig==4===3
[MCU2_0] 15.840122 s: [dans] Board_ethConfigCpsw9gEnet2--4
[MCU2_0] 15.840152 s: ETHFW: EthFwBoard_init: dans--EthFwBoard_init---1
[MCU2_0] 15.840191 s: ETHFW: EthFwBoard_configSerdesBridge: dans=EthFwBoard_configSerdesBridge
[MCU2_0] 15.840820 s: [dans] Board_serdesCfgSgmii ==2
[MCU2_0] 15.840848 s: [dans] Board_CfgSgmii_serdes1 start
[MCU2_0] 15.840878 s: Board_CfgSgmii_serdes1 82
[MCU2_0] 15.840904 s: Board_CfgSgmii_serdes1 104
[MCU2_0] 15.840945 s: Board_CfgSgmii_serdes1 107
[MCU2_0] 15.840975 s: Board_CfgSgmii_serdes1 134
[MCU2_0] 15.841019 s: Board_CfgSgmii_serdes1 142
[MCU2_0] 15.841045 s: Board_CfgSgmii_serdes1 148
[MCU2_0] 15.841070 s: Board_CfgSgmii_serdes1 152
[MCU2_0] 15.841130 s: Board_CfgSgmii_serdes1 161
[MCU2_0] 15.841398 s: Board_CfgSgmii_serdes1 169
[MCU2_0] 15.841417 s: [dans] Board_CfgSgmii_serdes1 end
[MCU2_0] 15.841448 s: [dans] Board_cpsw9gMacModeConfig==0===3
[MCU2_0] 15.843923 s: dans--appUdmaGetObj
[MCU2_0] 15.843953 s: dans--000000000000
[MCU2_0] 15.843986 s: dans--EthApp_initEthFw
[MCU2_0] 15.844050 s: ETHFW: dans--Warning: Using 6 random MAC address(es)
[MCU2_0] 15.844084 s: ETHFW: Warning: Using 6 MAC address(es) from static pool
[MCU2_0] 15.844217 s: ETHFW: dans--CPSW recovery is not enabled
[MCU2_0] 15.844268 s: ETHFW: dans--EthFwMcast_init
[MCU2_0] 15.844299 s: ETHFW: dans--EthFwMcast_getSharedMcastCfg
[MCU2_0] 15.844326 s: ETHFW: dans--Shared multicasts:
[MCU2_0] 15.844355 s: ETHFW: dans-- 01:00:5e:00:00:01
[MCU2_0] 15.844383 s: ETHFW: dans-- 01:00:5e:00:00:fb
[MCU2_0] 15.844409 s: ETHFW: dans-- 01:00:5e:00:00:fc
[MCU2_0] 15.844433 s: ETHFW: dans-- 33:33:00:00:00:01
[MCU2_0] 15.844459 s: ETHFW: dans-- 33:33:ff:1d:92:c2
[MCU2_0] 15.844484 s: ETHFW: dans-- 01:80:c2:00:00:00
[MCU2_0] 15.844509 s: ETHFW: dans-- 01:80:c2:00:00:03
[MCU2_0] 15.844531 s: ETHFW: dans--Reserved multicasts:
[MCU2_0] 15.844558 s: ETHFW: dans-- 01:80:c2:00:00:0e
[MCU2_0] 15.844584 s: ETHFW: dans-- 01:1b:19:00:00:00
[MCU2_0] 15.844707 s: dans---MCM_GET_HANDLE
[MCU2_0] 15.844738 s: dans--EnetMcm: CPSW_9G on MAIN NAVSS
[MCU2_0] 15.849479 s: Cpsw_open: dans=Cpsw_open
[MCU2_0] 15.849514 s:
[MCU2_0] 15.849590 s: EnetMod_open: dans=EnetMod_open
[MCU2_0] 15.849613 s:
[MCU2_0] 15.849681 s: EnetMod_open: dans=EnetMod_open end
[MCU2_0] 15.849702 s:
[MCU2_0] 15.849717 s: EnetMod_open: dans=EnetMod_open
[MCU2_0] 15.849736 s:
[MCU2_0] 15.853792 s: EnetMod_open: dans=EnetMod_open end
[MCU2_0] 15.853826 s:
[MCU2_0] 15.853846 s: EnetMod_open: dans=EnetMod_open
[MCU2_0] 15.853866 s:
[MCU2_0] 15.853889 s: EnetMod_open: dans=EnetMod_open end
[MCU2_0] 15.853909 s:
[MCU2_0] 15.853924 s: EnetMod_open: dans=EnetMod_open
[MCU2_0] 15.853943 s:
[MCU2_0] 15.853959 s: Mdio_open: dans=Mdio_open
[MCU2_0] 15.853977 s:
[MCU2_0] 15.854005 s: EnetMod_open: dans=EnetMod_open end
[MCU2_0] 15.854026 s:
[MCU2_0] 15.854041 s: EnetMod_open: dans=EnetMod_open
[MCU2_0] 15.854059 s:
[MCU2_0] 15.855078 s: EnetMod_open: dans=EnetMod_open end
[MCU2_0] 15.855101 s:
[MCU2_0] 15.855687 s: EnetMod_open: dans=EnetMod_open
[MCU2_0] 15.855720 s:
[MCU2_0] 15.855762 s: EnetMod_open: dans=EnetMod_open end
[MCU2_0] 15.855786 s:
[MCU2_0] 15.856422 s: dans111---PHY 0 is alive
[MCU2_0] 15.856455 s: dans111---PHY 1 is alive
[MCU2_0] 15.856477 s: dans111---PHY 2 is no alive
[MCU2_0] 15.856499 s: dans111---PHY 3 is no alive
[MCU2_0] 15.856519 s: dans111---PHY 4 is no alive
[MCU2_0] 15.856539 s: dans111---PHY 5 is no alive
[MCU2_0] 15.856559 s: dans111---PHY 6 is no alive
[MCU2_0] 15.856579 s: dans111---PHY 7 is no alive
[MCU2_0] 15.856600 s: dans111---PHY 8 is no alive
[MCU2_0] 15.856619 s: dans111---PHY 9 is no alive
[MCU2_0] 15.856640 s: dans111---PHY 10 is no alive
[MCU2_0] 15.856660 s: dans111---PHY 11 is no alive
[MCU2_0] 15.856681 s: dans111---PHY 12 is no alive
[MCU2_0] 15.856701 s: dans111---PHY 13 is no alive
[MCU2_0] 15.856722 s: dans111---PHY 14 is no alive
[MCU2_0] 15.856742 s: dans111---PHY 15 is no alive
[MCU2_0] 15.856762 s: dans111---PHY 16 is no alive
[MCU2_0] 15.856783 s: dans111---PHY 17 is no alive
[MCU2_0] 15.856804 s: dans111---PHY 18 is no alive
[MCU2_0] 15.856824 s: dans111---PHY 19 is no alive
[MCU2_0] 15.856845 s: dans111---PHY 20 is no alive
[MCU2_0] 15.856866 s: dans111---PHY 21 is no alive
[MCU2_0] 15.856886 s: dans111---PHY 22 is no alive
[MCU2_0] 15.856906 s: dans111---PHY 23 is no alive
[MCU2_0] 15.856927 s: dans111---PHY 24 is no alive
[MCU2_0] 15.856947 s: dans111---PHY 25 is no alive
[MCU2_0] 15.856967 s: dans111---PHY 26 is no alive
[MCU2_0] 15.856988 s: dans111---PHY 27 is no alive
[MCU2_0] 15.857008 s: dans111---PHY 28 is no alive
[MCU2_0] 15.857029 s: dans111---PHY 29 is no alive
[MCU2_0] 15.857049 s: dans111---PHY 30 is no alive
[MCU2_0] 15.857078 s: ETHFW: EthFwBoard_setPortCfg: dans=0EthFwBoard_setPortCfg =0
[MCU2_0] 15.857112 s: EnetPhy_initCfg: dans=EnetPhy_initCfg =0
[MCU2_0] 15.857134 s:
[MCU2_0] 15.857151 s: ETHFW: EthFwBoard_findPortCfg: dans=EthFwBoard_findPortCfg
[MCU2_0] 15.857185 s: ETHFW: EthFwBoard_findPortCfg: dans=EthFwBoard_findPortCfg--1
[MCU2_0] 15.857217 s: ETHFW: EthFwBoard_setPortCfg: dans=3EthFwBoard_setPortCfg =1
[MCU2_0] 15.857247 s: ETHFW: EthFwBoard_setPortCfg: dans=2EthFwBoard_setPortCfg =1
[MCU2_0] 15.857284 s: Cpsw_ioctlInternal: dans=ENET_PER_IOCTL_OPEN_PORT_LINK
[MCU2_0] 15.857310 s:
[MCU2_0] 15.857328 s: Cpsw_ioctlInternal: dans=ENET_PER_IOCTL_OPEN_PORT_LINK =1
[MCU2_0] 15.857353 s:
[MCU2_0] 15.857370 s: Cpsw_openPortLink: dans=Cpsw_openPortLink
[MCU2_0] 15.857391 s:
[MCU2_0] 15.857408 s: Cpsw_openPortLink: dans=Cpsw_openPortLink =1
[MCU2_0] 15.857430 s:
[MCU2_0] 15.857453 s: EnetPhyMdioDflt_getPhyMdio: dans=EnetPhyMdioDflt_getPhyMdio
[MCU2_0] 15.857478 s:
[MCU2_0] 15.857496 s: Cpsw_openPortLinkWithPhy: dans=Cpsw_openPortLinkWithPhy =1
[MCU2_0] 15.857521 s:
[MCU2_0] 15.857535 s: EnetMod_open: dans=EnetMod_open
[MCU2_0] 15.857554 s:
[MCU2_0] 15.857713 s: CpswMacPort_setSgmiiInterface: MAC 1: SERDES PLL is not locked
[MCU2_0] 15.857743 s: : -9
[MCU2_0] 15.857759 s: CpswMacPort_setSgmiiInterface:
[MCU2_0] 15.857779 s: : -1
[MCU2_0] 15.857799 s: Assertion @ Line: 2320 in src/mod/cpsw_macport.c: false
[MCU2_1] 4.773036 s: CIO: Init ... Done !!!
[MCU2_1] 4.773093 s: ### CPU Frequency = 1000000000 Hz
[MCU2_1] 4.773119 s: CPU is running FreeRTOS

After modifying according to your description,Same error log message：

root@j784s4-evm:~# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500
inet6 fe80::2ab5:e8ff:feda:3266 prefixlen 64 scopeid 0x20<link>
ether 28:b5:e8:da:32:66 txqueuelen 1000 (Ethernet)
RX packets 0 bytes 0 (0.0 B)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 19 bytes 2686 (2.6 KiB)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

eth1: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500
inet6 fe80::b8da:41ff:fe16:18d0 prefixlen 64 scopeid 0x20<link>
ether ba:da:41:16:18:d0 txqueuelen 1000 (Ethernet)
RX packets 277 bytes 20340 (19.8 KiB)
RX errors 0 dropped 255 overruns 0 frame 0
TX packets 21 bytes 3090 (3.0 KiB)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING> mtu 65536
inet 127.0.0.1 netmask 255.0.0.0
inet6 ::1 prefixlen 128 scopeid 0x10<host>
loop txqueuelen 1000 (Local Loopback)
RX packets 92 bytes 7654 (7.4 KiB)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 92 bytes 7654 (7.4 KiB)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

root@j784s4-evm:~# /opt/vision_apps/vision_apps_init.sh
root@j784s4-evm:~# [MCU2_0] 4.749329 s: CIO: Init ... Done !!!
[MCU2_0] 4.749365 s: ### CPU Frequency = 1000000000 Hz
[MCU2_0] 4.749391 s: CPU is running FreeRTOS
[MCU2_0] 4.749407 s: APP: Init ... !!!
[MCU2_0] 4.749441 s: SCICLIENT: Init ... !!!
[MCU2_0] 4.749564 s: SCICLIENT: DMSC FW version [9.1.2--v09.01.02 (Kool Koala)]
[MCU2_0] 4.749594 s: SCICLIENT: DMSC FW revision 0x9
[MCU2_0] 4.749613 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_0] 4.749633 s: SCICLIENT: Init ... Done !!!
[MCU2_0] 4.749651 s: UDMA: Init ... !!!
[MCU2_0] 4.750516 s: UDMA: Init ... Done !!!
[MCU2_0] 4.750548 s: UDMA: Init for CSITX/CSIRX ... !!!
[MCU2_0] 4.750972 s: UDMA: Init for CSITX/CSIRX ... Done !!!
[MCU2_0] 4.751001 s: MEM: Init ... !!!
[MCU2_0] 4.751024 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ bc800000 of size 268435456 bytes !!!
[MCU2_0] 4.751065 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 60000000 of size 262144 bytes !!!
[MCU2_0] 4.751099 s: MEM: Init ... Done !!!
[MCU2_0] 4.751115 s: IPC: Init ... !!!
[MCU2_0] 4.751148 s: IPC: 11 CPUs participating in IPC !!!
[MCU2_0] 4.751185 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_0] 15.066119 s: IPC: HLOS is ready !!!
[MCU2_0] 15.073320 s: IPC: Init ... Done !!!
[MCU2_0] 15.073368 s: APP: Syncing with 10 CPUs ... !!!
[MCU2_0] 15.838096 s: APP: Syncing with 10 CPUs ... Done !!!
[MCU2_0] 15.838130 s: REMOTE_SERVICE: Init ... !!!
[MCU2_0] 15.838952 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_0] 15.838996 s: dans--ETHFW: Init ... !!!
[MCU2_0] 15.839029 s: dans--EthFwTrace_init
[MCU2_0] 15.839061 s: ETHFW: EthFwBoard_init: dans--EthFwBoard_init
[MCU2_0] 15.839590 s: [dans] Board_init
[MCU2_0] 15.839614 s: [dans] Board_sysInit
[MCU2_0] 15.839805 s: [dans] BOARD_INIT_ENETCTRL_CPSW9G
[MCU2_0] 15.839841 s: [dans] Board_ethConfigCpsw9g==2,==0
[MCU2_0] 15.839862 s: [dans] Board_ethConfigCpsw9gEnet1
[MCU2_0] 15.839883 s: [dans] Board_ethConfigCpsw9gEnet1--0
[MCU2_0] 15.839913 s: [dans] Board_cpsw9gMacModeConfig==0===3
[MCU2_0] 15.839945 s: [dans] Board_ethConfigCpsw9gEnet1--0
[MCU2_0] 15.839974 s: [dans] Board_cpsw9gMacModeConfig==2===3
[MCU2_0] 15.840005 s: [dans] Board_ethConfigCpsw9gEnet2--2
[MCU2_0] 15.840034 s: [dans] Board_cpsw9gMacModeConfig==3===3
[MCU2_0] 15.840063 s: [dans] Board_ethConfigCpsw9gEnet2--3
[MCU2_0] 15.840092 s: [dans] Board_cpsw9gMacModeConfig==4===3
[MCU2_0] 15.840122 s: [dans] Board_ethConfigCpsw9gEnet2--4
[MCU2_0] 15.840152 s: ETHFW: EthFwBoard_init: dans--EthFwBoard_init---1
[MCU2_0] 15.840191 s: ETHFW: EthFwBoard_configSerdesBridge: dans=EthFwBoard_configSerdesBridge
[MCU2_0] 15.840820 s: [dans] Board_serdesCfgSgmii ==2
[MCU2_0] 15.840848 s: [dans] Board_CfgSgmii_serdes1 start
[MCU2_0] 15.840878 s: Board_CfgSgmii_serdes1 82
[MCU2_0] 15.840904 s: Board_CfgSgmii_serdes1 104
[MCU2_0] 15.840945 s: Board_CfgSgmii_serdes1 107
[MCU2_0] 15.840975 s: Board_CfgSgmii_serdes1 134
[MCU2_0] 15.841019 s: Board_CfgSgmii_serdes1 142
[MCU2_0] 15.841045 s: Board_CfgSgmii_serdes1 148
[MCU2_0] 15.841070 s: Board_CfgSgmii_serdes1 152
[MCU2_0] 15.841130 s: Board_CfgSgmii_serdes1 161
[MCU2_0] 15.841398 s: Board_CfgSgmii_serdes1 169
[MCU2_0] 15.841417 s: [dans] Board_CfgSgmii_serdes1 end
[MCU2_0] 15.841448 s: [dans] Board_cpsw9gMacModeConfig==0===3
[MCU2_0] 15.843923 s: dans--appUdmaGetObj
[MCU2_0] 15.843953 s: dans--000000000000
[MCU2_0] 15.843986 s: dans--EthApp_initEthFw
[MCU2_0] 15.844050 s: ETHFW: dans--Warning: Using 6 random MAC address(es)
[MCU2_0] 15.844084 s: ETHFW: Warning: Using 6 MAC address(es) from static pool
[MCU2_0] 15.844217 s: ETHFW: dans--CPSW recovery is not enabled
[MCU2_0] 15.844268 s: ETHFW: dans--EthFwMcast_init
[MCU2_0] 15.844299 s: ETHFW: dans--EthFwMcast_getSharedMcastCfg
[MCU2_0] 15.844326 s: ETHFW: dans--Shared multicasts:
[MCU2_0] 15.844355 s: ETHFW: dans-- 01:00:5e:00:00:01
[MCU2_0] 15.844383 s: ETHFW: dans-- 01:00:5e:00:00:fb
[MCU2_0] 15.844409 s: ETHFW: dans-- 01:00:5e:00:00:fc
[MCU2_0] 15.844433 s: ETHFW: dans-- 33:33:00:00:00:01
[MCU2_0] 15.844459 s: ETHFW: dans-- 33:33:ff:1d:92:c2
[MCU2_0] 15.844484 s: ETHFW: dans-- 01:80:c2:00:00:00
[MCU2_0] 15.844509 s: ETHFW: dans-- 01:80:c2:00:00:03
[MCU2_0] 15.844531 s: ETHFW: dans--Reserved multicasts:
[MCU2_0] 15.844558 s: ETHFW: dans-- 01:80:c2:00:00:0e
[MCU2_0] 15.844584 s: ETHFW: dans-- 01:1b:19:00:00:00
[MCU2_0] 15.844707 s: dans---MCM_GET_HANDLE
[MCU2_0] 15.844738 s: dans--EnetMcm: CPSW_9G on MAIN NAVSS
[MCU2_0] 15.849479 s: Cpsw_open: dans=Cpsw_open
[MCU2_0] 15.849514 s:
[MCU2_0] 15.849590 s: EnetMod_open: dans=EnetMod_open
[MCU2_0] 15.849613 s:
[MCU2_0] 15.849681 s: EnetMod_open: dans=EnetMod_open end
[MCU2_0] 15.849702 s:
[MCU2_0] 15.849717 s: EnetMod_open: dans=EnetMod_open
[MCU2_0] 15.849736 s:
[MCU2_0] 15.853792 s: EnetMod_open: dans=EnetMod_open end
[MCU2_0] 15.853826 s:
[MCU2_0] 15.853846 s: EnetMod_open: dans=EnetMod_open
[MCU2_0] 15.853866 s:
[MCU2_0] 15.853889 s: EnetMod_open: dans=EnetMod_open end
[MCU2_0] 15.853909 s:
[MCU2_0] 15.853924 s: EnetMod_open: dans=EnetMod_open
[MCU2_0] 15.853943 s:
[MCU2_0] 15.853959 s: Mdio_open: dans=Mdio_open
[MCU2_0] 15.853977 s:
[MCU2_0] 15.854005 s: EnetMod_open: dans=EnetMod_open end
[MCU2_0] 15.854026 s:
[MCU2_0] 15.854041 s: EnetMod_open: dans=EnetMod_open
[MCU2_0] 15.854059 s:
[MCU2_0] 15.855078 s: EnetMod_open: dans=EnetMod_open end
[MCU2_0] 15.855101 s:
[MCU2_0] 15.855687 s: EnetMod_open: dans=EnetMod_open
[MCU2_0] 15.855720 s:
[MCU2_0] 15.855762 s: EnetMod_open: dans=EnetMod_open end
[MCU2_0] 15.855786 s:
[MCU2_0] 15.856422 s: dans111---PHY 0 is alive
[MCU2_0] 15.856455 s: dans111---PHY 1 is alive
[MCU2_0] 15.856477 s: dans111---PHY 2 is no alive
[MCU2_0] 15.856499 s: dans111---PHY 3 is no alive
[MCU2_0] 15.856519 s: dans111---PHY 4 is no alive
[MCU2_0] 15.856539 s: dans111---PHY 5 is no alive
[MCU2_0] 15.856559 s: dans111---PHY 6 is no alive
[MCU2_0] 15.856579 s: dans111---PHY 7 is no alive
[MCU2_0] 15.856600 s: dans111---PHY 8 is no alive
[MCU2_0] 15.856619 s: dans111---PHY 9 is no alive
[MCU2_0] 15.856640 s: dans111---PHY 10 is no alive
[MCU2_0] 15.856660 s: dans111---PHY 11 is no alive
[MCU2_0] 15.856681 s: dans111---PHY 12 is no alive
[MCU2_0] 15.856701 s: dans111---PHY 13 is no alive
[MCU2_0] 15.856722 s: dans111---PHY 14 is no alive
[MCU2_0] 15.856742 s: dans111---PHY 15 is no alive
[MCU2_0] 15.856762 s: dans111---PHY 16 is no alive
[MCU2_0] 15.856783 s: dans111---PHY 17 is no alive
[MCU2_0] 15.856804 s: dans111---PHY 18 is no alive
[MCU2_0] 15.856824 s: dans111---PHY 19 is no alive
[MCU2_0] 15.856845 s: dans111---PHY 20 is no alive
[MCU2_0] 15.856866 s: dans111---PHY 21 is no alive
[MCU2_0] 15.856886 s: dans111---PHY 22 is no alive
[MCU2_0] 15.856906 s: dans111---PHY 23 is no alive
[MCU2_0] 15.856927 s: dans111---PHY 24 is no alive
[MCU2_0] 15.856947 s: dans111---PHY 25 is no alive
[MCU2_0] 15.856967 s: dans111---PHY 26 is no alive
[MCU2_0] 15.856988 s: dans111---PHY 27 is no alive
[MCU2_0] 15.857008 s: dans111---PHY 28 is no alive
[MCU2_0] 15.857029 s: dans111---PHY 29 is no alive
[MCU2_0] 15.857049 s: dans111---PHY 30 is no alive
[MCU2_0] 15.857078 s: ETHFW: EthFwBoard_setPortCfg: dans=0EthFwBoard_setPortCfg =0
[MCU2_0] 15.857112 s: EnetPhy_initCfg: dans=EnetPhy_initCfg =0
[MCU2_0] 15.857134 s:
[MCU2_0] 15.857151 s: ETHFW: EthFwBoard_findPortCfg: dans=EthFwBoard_findPortCfg
[MCU2_0] 15.857185 s: ETHFW: EthFwBoard_findPortCfg: dans=EthFwBoard_findPortCfg--1
[MCU2_0] 15.857217 s: ETHFW: EthFwBoard_setPortCfg: dans=3EthFwBoard_setPortCfg =1
[MCU2_0] 15.857247 s: ETHFW: EthFwBoard_setPortCfg: dans=2EthFwBoard_setPortCfg =1
[MCU2_0] 15.857284 s: Cpsw_ioctlInternal: dans=ENET_PER_IOCTL_OPEN_PORT_LINK
[MCU2_0] 15.857310 s:
[MCU2_0] 15.857328 s: Cpsw_ioctlInternal: dans=ENET_PER_IOCTL_OPEN_PORT_LINK =1
[MCU2_0] 15.857353 s:
[MCU2_0] 15.857370 s: Cpsw_openPortLink: dans=Cpsw_openPortLink
[MCU2_0] 15.857391 s:
[MCU2_0] 15.857408 s: Cpsw_openPortLink: dans=Cpsw_openPortLink =1
[MCU2_0] 15.857430 s:
[MCU2_0] 15.857453 s: EnetPhyMdioDflt_getPhyMdio: dans=EnetPhyMdioDflt_getPhyMdio
[MCU2_0] 15.857478 s:
[MCU2_0] 15.857496 s: Cpsw_openPortLinkWithPhy: dans=Cpsw_openPortLinkWithPhy =1
[MCU2_0] 15.857521 s:
[MCU2_0] 15.857535 s: EnetMod_open: dans=EnetMod_open
[MCU2_0] 15.857554 s:
[MCU2_0] 15.857713 s: CpswMacPort_setSgmiiInterface: MAC 1: SERDES PLL is not locked
[MCU2_0] 15.857743 s: : -9
[MCU2_0] 15.857759 s: CpswMacPort_setSgmiiInterface:
[MCU2_0] 15.857779 s: : -1
[MCU2_0] 15.857799 s: Assertion @ Line: 2320 in src/mod/cpsw_macport.c: false
[MCU2_1] 4.773036 s: CIO: Init ... Done !!!
[MCU2_1] 4.773093 s: ### CPU Frequency = 1000000000 Hz
[MCU2_1] 4.773119 s: CPU is running FreeRTOS

Hi,

Can you please confirm, have you commented default SGMII configuration in SDK or not?
If not it might also configures Port-1 in SGMII, can you please comment out default SGMII configuration and check once.

Best Regards,
Sudheer

I have already annotated the original one（SERDES2）.

now code below:

Hi,

jin zhu said:

serdesLane0EnableParams.laneCtrlRate[1] = CSL_SERDES_LANE_FULL_RATE;
serdesLane0EnableParams.loopbackMode[1] = CSL_SERDES_LOOPBACK_DISABLED;

Lane control for Lane2 is not added, you are using Lane2 for Port-1. 
So, you need to have below.

serdesLane0EnableParams.laneCtrlRate[2] = CSL_SERDES_LANE_FULL_RATE;
serdesLane0EnableParams.loopbackMode[2] = CSL_SERDES_LOOPBACK_DISABLED;

Also, you no need have SerDes IP select for all lanes as your lanemask is 0x4 i.e. only Lane 2 to be enabled i.e. below will be fine, you can remove rest all.
for details please refer to defautl sgmii configuration from "Board_CfgSgmii" how SerDes is configured.

/* Select the IP type, IP instance num, Serdes Lane Number */
CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
serdesLane0EnableParams.phyType,
serdesLane0EnableParams.phyInstanceNum,
serdesLane0EnableParams.serdesInstance,
2U);

Best Regards,
Sudheer

Hi,

Yes, above SerDes configuration and SerDes clocks looks OK.
PLL should have been locked.

Can you please check following SerDes register value.
0x000507E000

Best Regards,
Sudheer

log below:

root@j784s4-evm:/opt# devmem2 0x000507E000
/dev/mem opened.
Memory mapped at address 0xffff9c09d000.
Read at address 0x0507E000 (0xffff9c09d000): 0x00490011
root@j784s4-evm:/opt#

Hi,

Form above register dump,  it is clear that SerDes1 PLL is locked.

Can you please confirm is Port-1 configured for SGMII or not?
Can you please read 0x00104044 register.

Best Regards,
Sudheer

Can you please confirm is Port-1 configured for SGMII or not?

yes,The attachment contains all the change points（The above has been posted regarding the SerDes1 configuration）

diff --git a/ethfw/utils/board/src/j784s4/board_j784s4_evm.c b/ethfw/utils/board/src/j784s4/board_j784s4_evm.c
index ca06cd8d..8fc53bdc 100644
--- a/ethfw/utils/board/src/j784s4/board_j784s4_evm.c
+++ b/ethfw/utils/board/src/j784s4/board_j784s4_evm.c
@@ -193,14 +193,15 @@ static EthFwBoard_MacPortCfg gEthFw_qenetMacPortCfg[] =
.mii = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_QUAD_SERIAL_MAIN },
.phyCfg =
{
- .phyAddr = 16U,
+ .phyAddr = 1U,
.isStrapped = false,
.skipExtendedCfg = false,
.extendedCfg = NULL,
.extendedCfgSize = 0U,
},
- .sgmiiMode = ENET_MAC_SGMIIMODE_SGMII_WITH_PHY,
- .linkCfg = { ENET_SPEED_AUTO, ENET_DUPLEX_AUTO },
+ //.sgmiiMode = ENET_MAC_SGMIIMODE_SGMII_WITH_PHY,
+ .sgmiiMode = ENET_MAC_SGMIIMODE_SGMII_AUTONEG_MASTER,
+ .linkCfg = { ENET_SPEED_1GBIT, ENET_DUPLEX_FULL },
},
{ /* "P1" */
.macPort = ENET_MAC_PORT_3,
@@ -249,17 +250,17 @@ static EthFwBoard_MacPortCfg gEthFw_qenetMacPortCfg[] =
/* 1 x SGMII port in MAC-to-MAC mode using (SGMII) ENET bridge expansion board */
static EthFwBoard_MacPortCfg gEthFw_enetBridgeMacPortCfg =
{
- .macPort = ENET_MAC_PORT_2,
+ .macPort = ENET_MAC_PORT_1,
.mii = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_SERIAL },
.phyCfg =
{
- .phyAddr = ENETPHY_INVALID_PHYADDR,
+ .phyAddr = 1U,//ENETPHY_INVALID_PHYADDR,
.isStrapped = false,
.skipExtendedCfg = false,
.extendedCfg = NULL,
.extendedCfgSize = 0U,
},
- .sgmiiMode = ENET_MAC_SGMIIMODE_SGMII_FORCEDLINK,
+ .sgmiiMode = ENET_MAC_SGMIIMODE_SGMII_WITH_PHY,//ENET_MAC_SGMIIMODE_SGMII_FORCEDLINK,
.linkCfg = { ENET_SPEED_1GBIT, ENET_DUPLEX_FULL },
};

static void EthFwBoard_configSerdesBridge(void)
{
Board_initParams_t prms;
Board_STATUS boardStatus;
-
+ ETHFWTRACE_ERR(ETHFW_SOK, "dans=EthFwBoard_configSerdesBridge\r\n");
if (gEthFwBoard.serdesAllowed)
{
- Board_getInitParams(&prms);
- prms.enetBoardID = BOARD_ID_ENET2;
- prms.dualEnetCfg = false;
- Board_setInitParams(&prms);
+ // Board_getInitParams(&prms);
+ // prms.enetBoardID = BOARD_ID_ENET2;
+ // prms.dualEnetCfg = false;
+ // Board_setInitParams(&prms);

/* Configure SerDes clocks */
EthFwBoard_configTorrentClks();
@@ -529,7 +553,7 @@ static void EthFwBoard_configSerdesBridge(void)
EnetAppUtils_assert(boardStatus == BOARD_SOK);

/* Set MAC mode to SGMII */
- boardStatus = Board_cpsw9gMacModeConfig(ENET_MACPORT_NORM(ENET_MAC_PORT_2), SGMII);
+ boardStatus = Board_cpsw9gMacModeConfig(ENET_MACPORT_NORM(ENET_MAC_PORT_1), SGMII);
ETHFWTRACE_ERR_IF((boardStatus != BOARD_SOK), boardStatus,
"Failed to set SoC MAC mode");
EnetAppUtils_assert(boardStatus == BOARD_SOK);
@@ -542,8 +566,8 @@ static void EthFwBoard_configTorrentClks(void)
uint32_t clkId;
uint32_t clkRateHz;

- moduleId = TISCI_DEV_SERDES_10G2;
- clkId = TISCI_DEV_SERDES_10G2_CORE_REF_CLK;
+ moduleId = TISCI_DEV_SERDES_10G1;
+ clkId = TISCI_DEV_SERDES_10G1_CORE_REF_CLK;
clkRateHz = 100000000U;
EnetAppUtils_clkRateSet(moduleId, clkId, clkRateHz);

diff --git a/pdk_j784s4_09_01_00_22/packages/ti/board/src/j784s4_evm/board_ethernet_config.c b/pdk_j784s4_09_01_00_22/packages/ti/board/src/j784s4_evm/board_ethernet_config.c
index 03cfd44f..77f8e123 100644
--- a/pdk_j784s4_09_01_00_22/packages/ti/board/src/j784s4_evm/board_ethernet_config.c
+++ b/pdk_j784s4_09_01_00_22/packages/ti/board/src/j784s4_evm/board_ethernet_config.c
@@ -42,7 +42,8 @@
#include "board_ethernet_config.h"
#include "board_internal.h"
#include <ti/csl/cslr_mdio.h>
-
+//#include <ti/drv/uart/UART_stdio.h>
+// #include <utils/console_io/include/app_log.h>
extern Board_initParams_t gBoardInitParams;

/**
@@ -238,7 +239,7 @@ static Board_STATUS Board_ethConfigCpsw9gEnet1(void)
{
Board_STATUS status = BOARD_SOK;
uint8_t portNum;
-
+ printf("[dans] Board_ethConfigCpsw9gEnet1--0\n");
/* Configure the CPSW9G ENET1 QSGMII ports */
for(portNum = 0; portNum < BOARD_CPSW9G_PORT_MAX; portNum++)
{
@@ -250,13 +251,20 @@ static Board_STATUS Board_ethConfigCpsw9gEnet1(void)
/* These ports are ununsed by default ENET1 board configuration */
continue;
}
+ //else if (1U == portNum)
+ //{
+ // status = Board_cpsw9gMacModeConfig(portNum, SGMII);
+ // printf("[dans] Board_ethConfigCpsw9gEnet0--%d\n",portNum);
+ //}
else if (BOARD_CPSW9G_ENET1_QGMII_PORTNUM == portNum)
{
- status = Board_cpsw9gMacModeConfig(portNum, QSGMII);
+ status = Board_cpsw9gMacModeConfig(portNum, SGMII);
+ printf("[dans] Board_ethConfigCpsw9gEnet1--%d\n",portNum);
}
else
{
- status = Board_cpsw9gMacModeConfig(portNum, QSGMII_SUB);
+ status = Board_cpsw9gMacModeConfig(portNum, SGMII);
+ printf("[dans] Board_ethConfigCpsw9gEnet2--%d\n",portNum);
}

if(status != BOARD_SOK)
@@ -279,7 +287,7 @@ static Board_STATUS Board_ethConfigCpsw9gEnet2(void)
{
Board_STATUS status = BOARD_SOK;
uint8_t portNum;
-
+ printf("[dans] Board_ethConfigCpsw9gEnet2--0\n");
/* Configure the CPSW9G ENET2 QSGMII ports */
for(portNum = 0; portNum < BOARD_CPSW9G_PORT_MAX; portNum++)
{
@@ -572,7 +580,7 @@ Board_STATUS Board_cpsw9gMacModeConfig(uint32_t portNum, uint8_t mode)
uint32_t status;
uintptr_t modeSel;
uint32_t regData;
-
+ printf("[dans] Board_cpsw9gMacModeConfig==%d===%d\n",portNum,mode);
Board_ethCfgKickCtrl(BOARD_SOC_DOMAIN_MAIN, 0);

modeSel = CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_ENET1_CTRL + (portNum * 0x04);
@@ -604,7 +612,7 @@ Board_STATUS Board_cpsw9gMacModeConfig(uint32_t portNum, uint8_t mode)
Board_STATUS Board_ethConfigCpsw2g(void)
{
Board_STATUS status = BOARD_SOK;
-
+ printf("[dans] Board_ethConfigCpsw2g\n");
/* Configures the MCU Ethernet */
status = Board_cpsw2gMacModeConfig(RGMII);
if(status != BOARD_SOK)
@@ -625,6 +633,7 @@ Board_STATUS Board_ethConfigCpsw2g(void)
Board_STATUS Board_ethConfigCpsw2gMain(void)
{
Board_STATUS status = BOARD_SOK;
+ printf("[dans] Board_ethConfigCpsw2gMain\n");
/* Configures the CPSW2G Main Domain RGMII ports */
status = Board_cpsw2gMainMacModeConfig(RGMII);
if(status != BOARD_SOK)
@@ -652,22 +661,26 @@ Board_STATUS Board_ethConfigCpsw9g(void)
boardID = gBoardInitParams.enetBoardID;
enetCfg = gBoardInitParams.dualEnetCfg;

+ printf("[dans] Board_ethConfigCpsw9g==%d,==%d\n",boardID,enetCfg);
if(enetCfg == 0)
{
/* One of the ENET port can be used for USXGMII in this configuration */
if(boardID == BOARD_ID_ENET)
{
/* Configure ENET1 port for QSGMII and port2 can be used for USXGMII */
+ printf("[dans] Board_ethConfigCpsw9gEnet1\n");
status = Board_ethConfigCpsw9gEnet1();
}
else
{
/* Configure ENET2 port for QSGMII and port1 can be used for USXGMII */
+ printf("[dans] Board_ethConfigCpsw9gEnet2\n");
status = Board_ethConfigCpsw9gEnet2();
}
}
else
{
+ printf("[dans] Board_ethConfigCpsw9gEnet3\n");
/* Both ENET ports will be configured for QSGMII */
if(boardID == BOARD_ID_ENET)
{

diff --git a/vision_apps/utils/ethfw/src/app_ethfw_freertos.c b/vision_apps/utils/ethfw/src/app_ethfw_freertos.c
index 7a62e997..c1c8e6e1 100644
--- a/vision_apps/utils/ethfw/src/app_ethfw_freertos.c
+++ b/vision_apps/utils/ethfw/src/app_ethfw_freertos.c
@@ -165,9 +165,9 @@ static Enet_MacPort gEthAppPorts[] =
#endif
#elif defined(SOC_J784S4)
ENET_MAC_PORT_1, /* QSGMII main */
- ENET_MAC_PORT_3, /* QSGMII sub */
- ENET_MAC_PORT_4, /* QSGMII sub */
- ENET_MAC_PORT_5, /* QSGMII sub */
+ // ENET_MAC_PORT_3, /* QSGMII sub */
+ // ENET_MAC_PORT_4, /* QSGMII sub */
+ // ENET_MAC_PORT_5, /* QSGMII sub */
#endif
};

@@ -465,7 +466,9 @@ int32_t appEthFwInit()
flags |= ETHFW_BOARD_QENET_ENABLE;
#endif
#elif defined(SOC_J784S4)
- flags |= (ETHFW_BOARD_QENET_ENABLE | ETHFW_BOARD_SERDES_CONFIG);
+ //flags |= (ETHFW_BOARD_QENET_ENABLE | ETHFW_BOARD_SERDES_CONFIG);
+ flags |= (ETHFW_BOARD_ENET_BRIDGE_ENABLE | ETHFW_BOARD_SERDES_CONFIG);
+
#endif

/* Board related initialization */

Can you please read 0x00104044 register.

root@j784s4-evm:~# devmem2 0x00104044
/dev/mem opened.
Memory mapped at address 0xffffb1cc9000.
Read at address 0x00104044 (0xffffb1cc9044): 0x00000003
root@j784s4-evm:~# devmem2 0x00104044
/dev/mem opened.
Memory mapped at address 0xffffa80e6000.
Read at address 0x00104044 (0xffffa80e6044): 0x00000003

Hi,

Above code change for MAC Port-1 is fine for SGMII.

Also, from register dump I could see Port-1 is configured in SGMII mode.

Also, from above SerDes register dump PLL0 is locked.

Can you check sgmii mode as below once.
.sgmiiMode = ENET_MAC_SGMIIMODE_SGMII_AUTONEG_MASTER,


Best Regards,
Sudheer

Hi,

Can you please check following register values.
0x00104090 -> SerDes1 Lane0 Control
0x00104094 -> SerDes1 Lane1 Control
0x00104098 -> SerDes1 Lane2 Control
0x0010409C -> SerDes1 Lane3 Control

Best Regards,
Sudheer

Read register:

root@j784s4-evm:~# devmem2 0x00104090
/dev/mem opened.
Memory mapped at address 0xffff9bc71000.
Read at address 0x00104090 (0xffff9bc71090): 0x00000001
root@j784s4-evm:~# devmem2 0x00104094
/dev/mem opened.
Memory mapped at address 0xffffb7964000.
Read at address 0x00104094 (0xffffb7964094): 0x00000001
root@j784s4-evm:~# devmem2 0x00104098
/dev/mem opened.
Memory mapped at address 0xffffa63e1000.
Read at address 0x00104098 (0xffffa63e1098): 0x00000000
root@j784s4-evm:~# devmem2 0x0010409C
/dev/mem opened.
Memory mapped at address 0xffffa0a01000.
Read at address 0x0010409C (0xffffa0a0109c): 0x00000001
root@j784s4-evm:~#

Hi,

Can you please check have you configuring the SerDes1 from Linux or U-boot? If so, can you disable the SerDes node from device tree.

As I could see other Pins of SerDes are configured for PCIe.

Also, can you please read below SerDes registers.
0x05070480
0x05070484
0x05070488
0x0507048C

0x050704C0
0x050704C4
0x050704C8
0x050704CC

0x05070500
0x05070504
0x05070508
0x0507050C

0x05070540
0x05070544
0x05070548
0x0507054C

Best Regards,
Sudheer

Can you please check have you configuring the SerDes1 from Linux or U-boot? If so, can you disable the SerDes node from device tree.

          Where can I modify this part? Can you provide a path or method.

read reg:

root@j784s4-evm:~#
root@j784s4-evm:~# devmem2 0x05070480
/dev/mem opened.
Memory mapped at address 0xffff9649a000.
Read at address 0x05070480 (0xffff9649a480): 0x30000000
root@j784s4-evm:~# devmem2 0x05070484
/dev/mem opened.
Memory mapped at address 0xffff8dc6f000.
Read at address 0x05070484 (0xffff8dc6f484): 0x00000000
root@j784s4-evm:~# devmem2 0x05070488
/dev/mem opened.
Memory mapped at address 0xffff9c504000.
Read at address 0x05070488 (0xffff9c504488): 0x00000000
root@j784s4-evm:~# devmem2 0x0507048C
/dev/mem opened.
Memory mapped at address 0xffff9ff3a000.
Read at address 0x0507048C (0xffff9ff3a48c): 0x00000012
root@j784s4-evm:~# devmem2 0x050704C0
/dev/mem opened.
Memory mapped at address 0xffff99abc000.
Read at address 0x050704C0 (0xffff99abc4c0): 0x30000000
root@j784s4-evm:~# devmem2 0x050704C4
/dev/mem opened.
Memory mapped at address 0xffffb3af7000.
Read at address 0x050704C4 (0xffffb3af74c4): 0x00000000
root@j784s4-evm:~# devmem2 0x050704C8
/dev/mem opened.
Memory mapped at address 0xffffba15b000.
Read at address 0x050704C8 (0xffffba15b4c8): 0x00000000
root@j784s4-evm:~# devmem2 0x050704CC
/dev/mem opened.
Memory mapped at address 0xffff8cba0000.
Read at address 0x050704CC (0xffff8cba04cc): 0x00000012
root@j784s4-evm:~# devmem2 0x05070500
/dev/mem opened.
Memory mapped at address 0xffff854a2000.
Read at address 0x05070500 (0xffff854a2500): 0x70800000
root@j784s4-evm:~# devmem2 0x05070504
/dev/mem opened.
Memory mapped at address 0xffffb25d6000.
Read at address 0x05070504 (0xffffb25d6504): 0x00010002
root@j784s4-evm:~# devmem2 0x05070508
/dev/mem opened.
Memory mapped at address 0xffff83a3a000.
Read at address 0x05070508 (0xffff83a3a508): 0x00000000
root@j784s4-evm:~# devmem2 0x0507050C
/dev/mem opened.
Memory mapped at address 0xffff9be3e000.
Read at address 0x0507050C (0xffff9be3e50c): 0x00000002
root@j784s4-evm:~# devmem2 0x05070540
/dev/mem opened.
Memory mapped at address 0xffff9ab3b000.
Read at address 0x05070540 (0xffff9ab3b540): 0x30000000
root@j784s4-evm:~# devmem2 0x05070544
/dev/mem opened.
Memory mapped at address 0xffff9da24000.
Read at address 0x05070544 (0xffff9da24544): 0x00000000
root@j784s4-evm:~# devmem2 0x05070548
/dev/mem opened.
Memory mapped at address 0xffffbef31000.
Read at address 0x05070548 (0xffffbef31548): 0x00000000
root@j784s4-evm:~# devmem2 0x0507054C
/dev/mem opened.
Memory mapped at address 0xffff9a306000.
Read at address 0x0507054C (0xffff9a30654c): 0x00000012
root@j784s4-evm:~#

add read reg:

root@j784s4-evm:~# devmem2 0x00104090
/dev/mem opened.
Memory mapped at address 0xffff9c109000.
Read at address 0x00104090 (0xffff9c109090): 0x00000001
root@j784s4-evm:~# devmem2 0x00104094
/dev/mem opened.
Memory mapped at address 0xffffab598000.
Read at address 0x00104094 (0xffffab598094): 0x00000001
root@j784s4-evm:~# devmem2 0x00104098
/dev/mem opened.
Memory mapped at address 0xffff804e6000.
Read at address 0x00104098 (0xffff804e6098): 0x00000000
root@j784s4-evm:~# devmem2 0x0010409c
/dev/mem opened.
Memory mapped at address 0xffff96421000.
Read at address 0x0010409C (0xffff9642109c): 0x00000001
root@j784s4-evm:~# devmem2 0x00104044
/dev/mem opened.
Memory mapped at address 0xffffba559000.
Read at address 0x00104044 (0xffffba559044): 0x00000003
root@j784s4-evm:~# devmem2 0x000507E000
/dev/mem opened.
Memory mapped at address 0xffffb786a000.
Read at address 0x0507E000 (0xffffb786a000): 0x00490011
root@j784s4-evm:~#

Hi,

jin zhu said:

Can you please check have you configuring the SerDes1 from Linux or U-boot? If so, can you disable the SerDes node from device tree.

          Where can I modify this part? Can you provide a path or method.

Are you running Linux on A72? If so, by default SerDes1 is configured for PCIe.

Please refer to below.


Please make status as "disabled" as show in below under "&serdes1" and "&serdes_wiz1" and rebuild "linux-dtbs" from Linux SDK.
status = "disabled";

Command for building device tree.
# make linux-dtbs

After building the Linux-dtbs, copy k3-j784s4-evm.dtb generated in above dts path to the your "rootfs/boot/dtb/ti" folder in filesystem.

Best Regards,
Sudheer

Hello, after making the changes, there is still an error message

Now I am using the demo code and after modifying the following points, I am able to read RTL9010:

diff --git a/ethfw/ethremotecfg/server/src/cpsw_proxy_server.c b/ethfw/ethremotecfg/server/src/cpsw_proxy_server.c
index afd62440..249088e6 100644
--- a/ethfw/ethremotecfg/server/src/cpsw_proxy_server.c
+++ b/ethfw/ethremotecfg/server/src/cpsw_proxy_server.c
@@ -2150,7 +2150,7 @@ int32_t CpswProxyServer_init(CpswProxyServer_Config_t *cfg)
         hServer->aleMacOnlyPortMask)
     {
         status = CPSWPROXYSERVER_EINVALIDPARAMS;
-        ETHFWTRACE_ERR(status, "MAC ports required for virtual MAC ports are not enabled");
+        ETHFWTRACE_ERR(status, " dans-MAC ports required for virtual MAC ports are not enabled");
     }
 
     hServer->aleSwitchOnlyPortMask = (hServer->alePortMask &
diff --git a/ethfw/ethremotecfg/server/src/ethfw_api.c b/ethfw/ethremotecfg/server/src/ethfw_api.c
index ff46d33f..b2c6ddb2 100644
--- a/ethfw/ethremotecfg/server/src/ethfw_api.c
+++ b/ethfw/ethremotecfg/server/src/ethfw_api.c
@@ -1124,7 +1124,7 @@ EthFw_Handle EthFw_init(Enet_Type enetType,
     gEthFwObj.monitor = config->monitorCfg;
     gEthFwObj.recoveryEn = ((gEthFwObj.monitor.openLwipDmaCb != NULL) &&
                             (gEthFwObj.monitor.closeLwipDmaCb != NULL));
-    ETHFWTRACE_INFO_IF(!gEthFwObj.recoveryEn, "CPSW recovery is not enabled");
+    ETHFWTRACE_INFO_IF(!gEthFwObj.recoveryEn, "dans--CPSW recovery is not enabled");
 #endif
 
 #if defined(ETHFW_GPTP_SUPPORT)
@@ -1495,6 +1495,10 @@ static void EthFw_initLinkArgs(EnetPer_PortLinkCfg *linkArgs,
         ETHFWTRACE_ERR(status, "Failed to set MAC port %u config", ENET_MACPORT_ID(macPort));
         EnetAppUtils_assert(false);
     }
+//    else
+//    {
+//        ETHFWTRACE_ERR(status, "dans-- to set MAC port %u config", ENET_MACPORT_ID(macPort));
+//    }
 
     for (i = 0U; i < gEthFwObj.numPorts; i++)
     {
diff --git a/ethfw/ethremotecfg/server/src/ethfw_mcast.c b/ethfw/ethremotecfg/server/src/ethfw_mcast.c
index 46c20cf0..97d7fe02 100644
--- a/ethfw/ethremotecfg/server/src/ethfw_mcast.c
+++ b/ethfw/ethremotecfg/server/src/ethfw_mcast.c
@@ -196,7 +196,7 @@ int32_t EthFwMcast_init(const EthFwMcast_Cfg *cfg,
     int32_t status = ETHFW_SOK;
 
     memset(&gEthFwMcastObj, 0, sizeof(gEthFwMcastObj));
-
+        //ETHFWTRACE_INFO("dans--EthFwMcast_init");
     /* Create mutex to protect MCAST configuration table */
     gEthFwMcastObj.hMutex = MutexP_create(&gEthFwMcastObj.mutexObj);
     if (gEthFwMcastObj.hMutex == NULL)
@@ -344,7 +344,7 @@ static int32_t EthFwMcast_getSharedMcastCfg(const EthFwMcast_SharedMcastCfg *cfg
     const uint8_t *macAddr;
     uint32_t i;
     int32_t status = ETHFW_SOK;
-
+        //ETHFWTRACE_INFO("dans--EthFwMcast_getSharedMcastCfg");
     if (cfg->numMcast > ETHFW_SHARED_MCAST_LIST_LEN)
     {
         status = ETHFW_EINVALIDPARAMS;
@@ -354,7 +354,7 @@ static int32_t EthFwMcast_getSharedMcastCfg(const EthFwMcast_SharedMcastCfg *cfg
 
     if (status == ETHFW_SOK)
     {
-        ETHFWTRACE_INFO("Shared multicasts:");
+        ETHFWTRACE_INFO("dans--Shared multicasts:");
 
         gEthFwMcastObj.sharedMcastTable.len = 0U;
 
@@ -366,7 +366,7 @@ static int32_t EthFwMcast_getSharedMcastCfg(const EthFwMcast_SharedMcastCfg *cfg
 
             if (EnetUtils_isMcastAddr(macAddr))
             {
-                ETHFWTRACE_INFO("  %02x:%02x:%02x:%02x:%02x:%02x",
+                ETHFWTRACE_INFO(" dans-- %02x:%02x:%02x:%02x:%02x:%02x",
                                 macAddr[0U], macAddr[1U], macAddr[2U],
                                 macAddr[3U], macAddr[4U], macAddr[5U]);
 
@@ -420,7 +420,7 @@ static int32_t EthFwMcast_getRsvdMcastCfg(const EthFwMcast_RsvdMcastCfg *cfg)
     if ((status == ETHFW_SOK) &&
         (cfg->numMcast > 0U))
     {
-        ETHFWTRACE_INFO("Reserved multicasts:");
+        ETHFWTRACE_INFO("dans--Reserved multicasts:");
 
         gEthFwMcastObj.rsvdMcastTable.len = 0U;
 
@@ -432,7 +432,7 @@ static int32_t EthFwMcast_getRsvdMcastCfg(const EthFwMcast_RsvdMcastCfg *cfg)
 
             if (EnetUtils_isMcastAddr(macAddr))
             {
-                ETHFWTRACE_INFO("  %02x:%02x:%02x:%02x:%02x:%02x",
+                ETHFWTRACE_INFO("dans--  %02x:%02x:%02x:%02x:%02x:%02x",
                                 macAddr[0U], macAddr[1U], macAddr[2U],
                                 macAddr[3U], macAddr[4U], macAddr[5U]);
 
diff --git a/ethfw/utils/board/src/j784s4/board_j784s4_evm.c b/ethfw/utils/board/src/j784s4/board_j784s4_evm.c
index ca06cd8d..d08fdf31 100644
--- a/ethfw/utils/board/src/j784s4/board_j784s4_evm.c
+++ b/ethfw/utils/board/src/j784s4/board_j784s4_evm.c
@@ -168,6 +168,8 @@ static void EthFwBoard_configSerdesBridge(void);
 
 static void EthFwBoard_configTorrentClks(void);
 
+static void EthFwBoard_configTorrentClks1(void);
+
 static void EthFwBoard_configCpswClocks(void);
 
 static uint32_t EthFwBoard_getMacAddrPoolEeprom(uint8_t macAddr[][ENET_MAC_ADDR_LEN],
@@ -188,19 +190,34 @@ extern pinmuxBoardCfg_t gEthFwPinmuxData[];
  *   4 x QSGMII ports in QEnet */
 static EthFwBoard_MacPortCfg gEthFw_qenetMacPortCfg[] =
 {
+    // {   /* "P0" */
+    //     .macPort   = ENET_MAC_PORT_1,
+    //     .mii       = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_QUAD_SERIAL_MAIN },
+    //     .phyCfg    =
+    //     {
+    //         .phyAddr         = 16U,
+    //         .isStrapped      = false,
+    //         .skipExtendedCfg = false,
+    //         .extendedCfg     = NULL,
+    //         .extendedCfgSize = 0U,
+    //     },
+    //     .sgmiiMode = ENET_MAC_SGMIIMODE_SGMII_WITH_PHY,
+    //     .linkCfg   = { ENET_SPEED_AUTO, ENET_DUPLEX_AUTO },
+    // },
     {   /* "P0" */
         .macPort   = ENET_MAC_PORT_1,
         .mii       = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_QUAD_SERIAL_MAIN },
         .phyCfg    =
         {
-            .phyAddr         = 16U,
+            .phyAddr         = 1U,
             .isStrapped      = false,
             .skipExtendedCfg = false,
             .extendedCfg     = NULL,
             .extendedCfgSize = 0U,
         },
-        .sgmiiMode = ENET_MAC_SGMIIMODE_SGMII_WITH_PHY,
-        .linkCfg   = { ENET_SPEED_AUTO, ENET_DUPLEX_AUTO },
+        //.sgmiiMode = ENET_MAC_SGMIIMODE_SGMII_WITH_PHY,
+        .sgmiiMode = ENET_MAC_SGMIIMODE_SGMII_AUTONEG_MASTER,
+        .linkCfg   = { ENET_SPEED_1GBIT, ENET_DUPLEX_FULL },
     },
     {   /* "P1" */
         .macPort   = ENET_MAC_PORT_3,
@@ -249,17 +266,17 @@ static EthFwBoard_MacPortCfg gEthFw_qenetMacPortCfg[] =
 /* 1 x SGMII port in MAC-to-MAC mode using (SGMII) ENET bridge expansion board */
 static EthFwBoard_MacPortCfg gEthFw_enetBridgeMacPortCfg =
 {
-    .macPort   = ENET_MAC_PORT_2,
+    .macPort   = ENET_MAC_PORT_1,
     .mii       = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_SERIAL },
     .phyCfg    =
     {
-        .phyAddr         = ENETPHY_INVALID_PHYADDR,
+        .phyAddr         = 1U,//ENETPHY_INVALID_PHYADDR,
         .isStrapped      = false,
         .skipExtendedCfg = false,
         .extendedCfg     = NULL,
         .extendedCfgSize = 0U,
     },
-    .sgmiiMode = ENET_MAC_SGMIIMODE_SGMII_FORCEDLINK,
+    .sgmiiMode = ENET_MAC_SGMIIMODE_SGMII_AUTONEG_MASTER,
     .linkCfg   = { ENET_SPEED_1GBIT, ENET_DUPLEX_FULL },
 };
 
@@ -272,6 +289,8 @@ int32_t EthFwBoard_init(uint32_t flags)
     Board_initCfg boardCfg = 0U;
     Board_STATUS boardStatus;
 
+    //ETHFWTRACE_ERR(ETHFW_SOK, "dans--EthFwBoard_init");
+            
     /* Save the functionality requested by app */
     gEthFwBoard.enetBridgeEnabled = ENET_NOT_ZERO(flags & ETHFW_BOARD_ENET_BRIDGE_ENABLE);
     gEthFwBoard.qenetEnabled  = ENET_NOT_ZERO(flags & ETHFW_BOARD_QENET_ENABLE);
@@ -295,6 +314,8 @@ int32_t EthFwBoard_init(uint32_t flags)
     /* Initialize board via board library */
     boardCfg |= BOARD_INIT_ENETCTRL_CPSW9G;
     boardStatus = Board_init(boardCfg);
+    //ETHFWTRACE_ERR(ETHFW_SOK, "dans--EthFwBoard_init---1");
+            
     ETHFWTRACE_ERR_IF((boardStatus != BOARD_SOK), boardStatus,
                       "Failed to initialize board");
     EnetAppUtils_assert(boardStatus == BOARD_SOK);
@@ -328,7 +349,7 @@ uint32_t EthFwBoard_getMacPorts(Enet_MacPort macPorts[ENET_MAC_PORT_NUM])
     uint32_t num = 0U;
     uint32_t req;
     uint32_t i;
-
+    //ETHFWTRACE_ERR(ETHFW_SOK, "dans=EthFwBoard_getMacPorts--0\r\n");
     memset(macPorts, 0, sizeof(*macPorts));
 
     if (gEthFwBoard.qenetEnabled && gEthFwBoard.qenetDetected)
@@ -342,6 +363,7 @@ uint32_t EthFwBoard_getMacPorts(Enet_MacPort macPorts[ENET_MAC_PORT_NUM])
 
     if (gEthFwBoard.enetBridgeEnabled)
     {
+        //ETHFWTRACE_ERR(ETHFW_SOK, "dans--EthFwBoard_getMacPorts---1");
         if (num < ENET_MAC_PORT_NUM)
         {
             macPorts[num++] = gEthFw_enetBridgeMacPortCfg.macPort;
@@ -355,9 +377,10 @@ static const EthFwBoard_MacPortCfg *EthFwBoard_findPortCfg(Enet_MacPort macPort)
 {
     const EthFwBoard_MacPortCfg *portCfg = NULL;
     uint32_t i;
-
+    //ETHFWTRACE_ERR(ETHFW_SOK, "dans=EthFwBoard_findPortCfg\r\n");
     if (gEthFwBoard.qenetEnabled && gEthFwBoard.qenetDetected)
     {
+           // ETHFWTRACE_ERR(ETHFW_SOK, "dans=EthFwBoard_findPortCfg---0.0\r\n");
         for (i = 0U; i < ENET_ARRAYSIZE(gEthFw_qenetMacPortCfg); i++)
         {
             if (gEthFw_qenetMacPortCfg[i].macPort == macPort)
@@ -370,6 +393,7 @@ static const EthFwBoard_MacPortCfg *EthFwBoard_findPortCfg(Enet_MacPort macPort)
 
     if ((portCfg == NULL) && gEthFwBoard.enetBridgeEnabled)
     {
+            //ETHFWTRACE_ERR(ETHFW_SOK, "dans=EthFwBoard_findPortCfg--1\r\n");
         if (gEthFw_enetBridgeMacPortCfg.macPort == macPort)
         {
             portCfg = &gEthFw_enetBridgeMacPortCfg;
@@ -387,7 +411,7 @@ int32_t EthFwBoard_setPortCfg(Enet_MacPort macPort,
 {
     const EthFwBoard_MacPortCfg *portCfg;
     int32_t status = ENET_ENOTFOUND;
-
+    //ETHFWTRACE_ERR(ETHFW_SOK, "dans=0EthFwBoard_setPortCfg =%d\r\n", phyCfg->phyAddr);
     CpswMacPort_initCfg(macCfg);
     EnetPhy_initCfg(phyCfg);
 
@@ -413,8 +437,9 @@ int32_t EthFwBoard_setPortCfg(Enet_MacPort macPort,
         macCfg->sgmiiMode = portCfg->sgmiiMode;
 
         status = ENET_SOK;
+        //ETHFWTRACE_ERR(ETHFW_SOK, "dans=3EthFwBoard_setPortCfg =%d\r\n", phyCfg->phyAddr);
     }
-
+    //ETHFWTRACE_ERR(ETHFW_SOK, "dans=2EthFwBoard_setPortCfg =%d\r\n", phyCfg->phyAddr);
     return status;
 }
 
@@ -468,7 +493,7 @@ static void EthFwBoard_configUart(void)
 static void EthFwBoard_configQenet(void)
 {
     Board_STATUS boardStatus;
-
+    //ETHFWTRACE_ERR(ETHFW_SOK, "dans=EthFwBoard_configQenet\r\n");
     if (gEthFwBoard.i2cAllowed)
     {
         /* Set MUX2 A <-> B2, needed for MDIO clock */
@@ -511,17 +536,17 @@ static void EthFwBoard_configSerdesBridge(void)
 {
     Board_initParams_t prms;
     Board_STATUS boardStatus;
-
+    //ETHFWTRACE_ERR(ETHFW_SOK, "dans=EthFwBoard_configSerdesBridge\r\n");
     if (gEthFwBoard.serdesAllowed)
     {
-        Board_getInitParams(&prms);
-        prms.enetBoardID = BOARD_ID_ENET2;
-        prms.dualEnetCfg = false;
-        Board_setInitParams(&prms);
+        // Board_getInitParams(&prms);
+        // prms.enetBoardID = BOARD_ID_ENET2;
+        // prms.dualEnetCfg = false;
+        // Board_setInitParams(&prms);
 
         /* Configure SerDes clocks */
-        EthFwBoard_configTorrentClks();
-
+        //EthFwBoard_configTorrentClks();
+		EthFwBoard_configTorrentClks1();
         /* Configure SerDes for SGMII functionality */
         boardStatus = Board_serdesCfgSgmii();
         ETHFWTRACE_ERR_IF((boardStatus != BOARD_SOK), boardStatus,
@@ -529,13 +554,27 @@ static void EthFwBoard_configSerdesBridge(void)
         EnetAppUtils_assert(boardStatus == BOARD_SOK);
 
         /* Set MAC mode to SGMII */
-        boardStatus = Board_cpsw9gMacModeConfig(ENET_MACPORT_NORM(ENET_MAC_PORT_2), SGMII);
+        boardStatus = Board_cpsw9gMacModeConfig(ENET_MACPORT_NORM(ENET_MAC_PORT_1), SGMII);
         ETHFWTRACE_ERR_IF((boardStatus != BOARD_SOK), boardStatus,
                           "Failed to set SoC MAC mode");
         EnetAppUtils_assert(boardStatus == BOARD_SOK);
     }
 }
 
+static void EthFwBoard_configTorrentClks1(void)
+{
+    uint32_t moduleId;
+    uint32_t clkId;
+    uint32_t clkRateHz;
+
+    moduleId  = TISCI_DEV_SERDES_10G1;
+    clkId     = TISCI_DEV_SERDES_10G1_CORE_REF_CLK;
+    clkRateHz = 100000000U;
+    EnetAppUtils_clkRateSet(moduleId, clkId, clkRateHz);
+
+    EnetAppUtils_setDeviceState(moduleId, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0U);
+}
+
 static void EthFwBoard_configTorrentClks(void)
 {
     uint32_t moduleId;
@@ -689,10 +728,10 @@ static uint32_t EthFwBoard_getMacAddrPoolStatic(uint8_t macAddr[][ENET_MAC_ADDR_
 
 #if defined(ETHFW_RAND_MACADDR_GEN)
     ETHFWTRACE_WARN_IF((allocCnt > 0U),
-                       "Warning: Using %u random MAC address(es)", allocCnt);
+                       "dans--Warning: Using %u random MAC address(es)", allocCnt);
 #else
     ETHFWTRACE_WARN_IF((allocCnt > 0U),
-                       "Warning: Using %u MAC address(es) from static pool", allocCnt);
+                       "dans--Warning: Using %u MAC address(es) from static pool", allocCnt);
 #endif
 
     return allocCnt;
diff --git a/pdk_j784s4_09_01_00_22/packages/ti/board/src/j784s4_evm/board_ethernet_config.c b/pdk_j784s4_09_01_00_22/packages/ti/board/src/j784s4_evm/board_ethernet_config.c
index 03cfd44f..23375307 100644
--- a/pdk_j784s4_09_01_00_22/packages/ti/board/src/j784s4_evm/board_ethernet_config.c
+++ b/pdk_j784s4_09_01_00_22/packages/ti/board/src/j784s4_evm/board_ethernet_config.c
@@ -248,6 +248,8 @@ static Board_STATUS Board_ethConfigCpsw9gEnet1(void)
              7U == portNum )
         {
             /* These ports are ununsed by default ENET1 board configuration */
+            status = Board_cpsw9gMacModeConfig(portNum, SGMII);
+            //printf("dans--Board_ethConfigCpsw9gEnet---\n\r");
             continue;
         }
         else if (BOARD_CPSW9G_ENET1_QGMII_PORTNUM == portNum)
diff --git a/pdk_j784s4_09_01_00_22/packages/ti/board/src/j784s4_evm/board_init.c b/pdk_j784s4_09_01_00_22/packages/ti/board/src/j784s4_evm/board_init.c
index 2f0976c1..582958bf 100644
--- a/pdk_j784s4_09_01_00_22/packages/ti/board/src/j784s4_evm/board_init.c
+++ b/pdk_j784s4_09_01_00_22/packages/ti/board/src/j784s4_evm/board_init.c
@@ -201,9 +201,10 @@ static Board_STATUS Board_sysDeinit(void)
 Board_STATUS Board_init(Board_initCfg cfg)
 {
     Board_STATUS ret = BOARD_SOK;
-
+    //printf("[dans] Board_init\n");
     if(!gBoardSysInitDone)
     {
+        //printf("[dans] Board_sysInit\n");
         Board_sysInit();
     }
 
@@ -218,7 +219,10 @@ Board_STATUS Board_init(Board_initCfg cfg)
         return ret;
 
     if (cfg & BOARD_INIT_ENETCTRL_CPSW9G)
+    {
+        //printf("[dans] BOARD_INIT_ENETCTRL_CPSW9G\n");
         ret = Board_ethConfigCpsw9g();
+    }
     if (ret != BOARD_SOK)
         return ret;
 
diff --git a/pdk_j784s4_09_01_00_22/packages/ti/board/src/j784s4_evm/board_serdes_cfg.c b/pdk_j784s4_09_01_00_22/packages/ti/board/src/j784s4_evm/board_serdes_cfg.c
index 1a841769..ae364de6 100644
--- a/pdk_j784s4_09_01_00_22/packages/ti/board/src/j784s4_evm/board_serdes_cfg.c
+++ b/pdk_j784s4_09_01_00_22/packages/ti/board/src/j784s4_evm/board_serdes_cfg.c
@@ -72,6 +72,111 @@ static Board_STATUS Board_serdesKickCtrl(uint32_t lockCtrl)
     return (status);
 }
 
+
+static Board_STATUS Board_CfgSgmii_serdes1(void)
+{
+    CSL_SerdesResult result;
+    CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;
+    CSL_SerdesLaneEnableParams serdesLane0EnableParams  = {0};
+    printf("[dans] Board_CfgSgmii_serdes1 start\n");
+    printf("%s %d \n",__func__,__LINE__);
+    memset(&serdesLane0EnableParams, 0, sizeof(serdesLane0EnableParams));
+
+    /* SGMII Config */
+    serdesLane0EnableParams.serdesInstance    = (CSL_SerdesInstance)CSL_TORRENT_SERDES1;
+    serdesLane0EnableParams.baseAddr          = CSL_WIZ16B8M4CT3_1_WIZ16B8M4CT3_BASE;
+    serdesLane0EnableParams.refClock          = CSL_SERDES_REF_CLOCK_100M;
+    serdesLane0EnableParams.refClkSrc         = CSL_SERDES_REF_CLOCK_INT0;
+    serdesLane0EnableParams.linkRate          = CSL_SERDES_LINK_RATE_1p25G;
+    serdesLane0EnableParams.numLanes          = 0x1;
+    serdesLane0EnableParams.laneMask          = 0x4;
+    serdesLane0EnableParams.SSC_mode          = CSL_SERDES_NO_SSC;
+    serdesLane0EnableParams.phyType           = CSL_SERDES_PHY_TYPE_SGMII;
+    serdesLane0EnableParams.operatingMode     = CSL_SERDES_FUNCTIONAL_MODE;
+    serdesLane0EnableParams.phyInstanceNum    = 0;//BOARD_SERDES_LANE_SELECT_CPSW;
+    serdesLane0EnableParams.pcieGenType        = CSL_SERDES_PCIE_GEN3;
+
+    serdesLane0EnableParams.laneCtrlRate[0]   = CSL_SERDES_LANE_FULL_RATE;
+    serdesLane0EnableParams.loopbackMode[0]   = CSL_SERDES_LOOPBACK_DISABLED;
+
+    serdesLane0EnableParams.laneCtrlRate[1]   = CSL_SERDES_LANE_FULL_RATE;
+    serdesLane0EnableParams.loopbackMode[1]   = CSL_SERDES_LOOPBACK_DISABLED;
+
+    serdesLane0EnableParams.laneCtrlRate[2] = CSL_SERDES_LANE_FULL_RATE;
+    serdesLane0EnableParams.loopbackMode[2] = CSL_SERDES_LOOPBACK_DISABLED;
+
+    serdesLane0EnableParams.laneCtrlRate[3] = CSL_SERDES_LANE_FULL_RATE;
+    serdesLane0EnableParams.loopbackMode[3] = CSL_SERDES_LOOPBACK_DISABLED;
+    printf("%s %d \n",__func__,__LINE__);
+
+    CSL_serdesPorReset(serdesLane0EnableParams.baseAddr);
+    printf("%s %d \n",__func__,__LINE__);
+
+    /* Select the IP type, IP instance num, Serdes Lane Number */
+    // CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
+    //                    serdesLane0EnableParams.phyType,
+    //                    serdesLane0EnableParams.phyInstanceNum,
+    //                    serdesLane0EnableParams.serdesInstance,
+    //                    0U);
+    // /* Select the IP type, IP instance num, Serdes Lane Number */
+    // CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
+    //                    serdesLane0EnableParams.phyType,
+    //                    serdesLane0EnableParams.phyInstanceNum,
+    //                    serdesLane0EnableParams.serdesInstance,
+    //                    1U);
+        /* Select the IP type, IP instance num, Serdes Lane Number */
+    CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
+                       serdesLane0EnableParams.phyType,
+                       serdesLane0EnableParams.phyInstanceNum,
+                       serdesLane0EnableParams.serdesInstance,
+                       2U);
+    //         /* Select the IP type, IP instance num, Serdes Lane Number */
+    // CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
+    //                    serdesLane0EnableParams.phyType,
+    //                    serdesLane0EnableParams.phyInstanceNum,
+    //                    serdesLane0EnableParams.serdesInstance,
+    //                    3U);
+
+    printf("%s %d \n",__func__,__LINE__);
+
+    result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,
+                                 serdesLane0EnableParams.baseAddr,
+                                 serdesLane0EnableParams.refClock,
+                                 serdesLane0EnableParams.refClkSrc,
+                                 serdesLane0EnableParams.serdesInstance,
+                                 serdesLane0EnableParams.phyType);
+    printf("%s %d \n",__func__,__LINE__);
+
+    if (result != CSL_SERDES_NO_ERR)
+    {
+        return BOARD_FAIL;
+    }
+    printf("%s %d \n",__func__,__LINE__);
+
+    /* Assert PHY reset and disable all lanes */
+    CSL_serdesDisablePllAndLanes(serdesLane0EnableParams.baseAddr, serdesLane0EnableParams.numLanes, serdesLane0EnableParams.laneMask);
+    printf("%s %d \n",__func__,__LINE__);
+
+    /* Load the Serdes Config File */
+    result = CSL_serdesEthernetInit(&serdesLane0EnableParams);
+    /* Return error if input params are invalid */
+    if (result != CSL_SERDES_NO_ERR)
+    {
+        return BOARD_FAIL;
+    }
+    printf("%s %d \n",__func__,__LINE__);
+
+    /* Common Lane Enable API for lane enable, pll enable etc */
+    laneRetVal = CSL_serdesLaneEnable(&serdesLane0EnableParams);
+    if (laneRetVal != 0)
+    {
+        return BOARD_FAIL;
+    }
+    printf("%s %d \n",__func__,__LINE__);
+    printf("[dans] Board_CfgSgmii_serdes1 end\n");
+    return BOARD_SOK;
+}
+
 static Board_STATUS Board_CfgSgmii(uint32_t boardID)
 {
     CSL_SerdesResult result;
@@ -79,7 +184,7 @@ static Board_STATUS Board_CfgSgmii(uint32_t boardID)
     CSL_SerdesLaneEnableParams serdesLaneEnableParams  = {0};
     uint32_t laneNum;
     uint32_t laneMask;
-
+    //printf("[dans] Board_CfgSgmii ==%d\n",boardID);
     if (boardID == BOARD_ID_ENET)
     {
         laneNum  = BOARD_SERDES_SGMII_ENET1_LANE_NUM;
@@ -328,21 +433,31 @@ Board_STATUS Board_serdesCfgSgmii(void)
     uint32_t boardID;
 
     boardID = gBoardInitParams.enetBoardID;
-
-    if ((boardID == BOARD_ID_ENET) ||
-        (boardID == BOARD_ID_ENET2))
-    {
-        /* Unlock MMR write access */
-        Board_serdesKickCtrl(0);
-
-        /* SGMII SERDES initializations */
+    //printf("[dans] Board_serdesCfgSgmii ==%d\n",boardID);
+    // if ((boardID == BOARD_ID_ENET) ||
+    //     (boardID == BOARD_ID_ENET2))
+    // {
+        // /* Unlock MMR write access */
+        // Board_serdesKickCtrl(0);
+        // printf("[dans] Board_serdesCfgSgmii---1\n");
+        // /* SGMII SERDES initializations */
+        #if 0
         ret = Board_CfgSgmii(boardID);
+        // Board_serdesKickCtrl(1); /* Lock MMR write access */
+        #endif
+        Board_serdesKickCtrl(0);/* Unlock MMR write access */
+        ret = Board_CfgSgmii_serdes1();
         Board_serdesKickCtrl(1); /* Lock MMR write access */
-    }
-    else
-    {
-        ret = BOARD_INVALID_PARAM;
-    }
+        if(ret != BOARD_SOK)
+        {
+            printf("[dans] error Board_serdesCfgSgmii==%d\n",boardID);
+            ret = Board_CfgSgmii(boardID);
+        }
+    // }
+    // else
+    // {
+    //     ret = BOARD_INVALID_PARAM;
+    // }
 
     return ret;
 }
diff --git a/pdk_j784s4_09_01_00_22/packages/ti/csl/src/ip/sgmii/V5/priv/csl_cpsgmii.c b/pdk_j784s4_09_01_00_22/packages/ti/csl/src/ip/sgmii/V5/priv/csl_cpsgmii.c
index 1c064d02..0f41ff2e 100644
--- a/pdk_j784s4_09_01_00_22/packages/ti/csl/src/ip/sgmii/V5/priv/csl_cpsgmii.c
+++ b/pdk_j784s4_09_01_00_22/packages/ti/csl/src/ip/sgmii/V5/priv/csl_cpsgmii.c
@@ -358,9 +358,11 @@ Uint32 CSL_SGMII_getRxTxSoftResetStatus
      @endverbatim
  * =============================================================================
  */
+#include <stdio.h>
 Uint32 CSL_SGMII_getSerdesPLLLockStatus(CSL_CpsgmiiRegs *hCpSgmiiRegs,
                                         Uint32 portNum)
 {
+    //sprintf("dans--CSL_SGMII_getSerdesPLLLockStatus222 ==%x\n",hCpSgmiiRegs[portNum].STATUS_REG);
     return CSL_FEXT (hCpSgmiiRegs[portNum].STATUS_REG, CPSGMII_STATUS_REG_LOCK);
 }
 
diff --git a/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/examples/utils/enet_mcm.c b/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/examples/utils/enet_mcm.c
index 3d012936..236677c7 100644
--- a/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/examples/utils/enet_mcm.c
+++ b/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/examples/utils/enet_mcm.c
@@ -785,7 +785,10 @@ static int32_t EnetMcm_enablePorts(EnetMcm_Handle hMcm)
         {
             if (alive == true)
             {
-                hMcm->print("PHY %d is alive\n", i);
+                hMcm->print("dans111---PHY %d is alive\n", i);
+            }else
+            {
+                hMcm->print("dans111---PHY %d is no  alive\n", i);
             }
         }
         else
@@ -932,7 +935,7 @@ static int32_t EnetMcm_open(EnetMcm_Handle hMcm)
     }
     else if (ENET_CPSW_9G == hMcm->enetType)
     {
-        hMcm->print("EnetMcm: CPSW_9G on MAIN NAVSS\n");
+        hMcm->print("dans--EnetMcm: CPSW_9G on MAIN NAVSS\n");
     }
     else if (ENET_CPSW_5G == hMcm->enetType)
     {
@@ -1111,6 +1114,7 @@ static void EnetMcm_serverTask(void * McmHandle,
         switch (msg.cmd)
         {
             case MCM_GET_HANDLE:
+            EnetAppUtils_print("dans---MCM_GET_HANDLE\n");
                 if (hMcm->refCnt == 0)
                 {
                     status = EnetMcm_open(hMcm);
diff --git a/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/soc/j7x/j784s4/enet_soc.c b/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/soc/j7x/j784s4/enet_soc.c
index 6d30be29..f7f4c360 100644
--- a/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/soc/j7x/j784s4/enet_soc.c
+++ b/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/soc/j7x/j784s4/enet_soc.c
@@ -1963,7 +1963,7 @@ static int32_t EnetSoc_getQsgmiiCfg(Enet_Type enetType,
     {
         qsgmiiSubPorts[i] = ENET_MAC_PORT_INV;
     }
-
+    //EnetSoc_assert(true, "dans--EnetSoc_getQsgmiiCfg %u\n", gEnetSoc_cpsw9g.macPortNum);
     for (i = 0U; i < gEnetSoc_cpsw9g.macPortNum; i++)
     {
         status = EnetSoc_getMacPortMii(enetType, instId, ENET_MACPORT_DENORM(i), &mii);
diff --git a/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/common/enet_phymdio_dflt.c b/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/common/enet_phymdio_dflt.c
index f11425e8..dab96ce6 100644
--- a/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/common/enet_phymdio_dflt.c
+++ b/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/common/enet_phymdio_dflt.c
@@ -122,6 +122,7 @@ static EnetPhy_Mdio gEnet_PhyMdioDflt =
 
 EnetPhy_MdioHandle EnetPhyMdioDflt_getPhyMdio(void)
 {
+    //ENETTRACE_INFO("dans=EnetPhyMdioDflt_getPhyMdio\r\n");
     return &gEnet_PhyMdioDflt;
 }
 
@@ -195,7 +196,7 @@ int32_t EnetPhyMdioDflt_isLinked(uint32_t phyAddr,
         ENETTRACE_ERR_IF(status != ENET_SOK, status,
                          "PHY %u: Failed to get link status", phyAddr);
     }
-
+    //ENETTRACE_INFO("dans=EnetPhyMdioDflt_isLinked---0\r\n");
     return status;
 }
 
@@ -381,7 +382,8 @@ int32_t EnetPhyMdioDflt_ioctl(EnetPhy_Handle hPhy,
                               Enet_IoctlPrms *prms)
 {
     int32_t status = ENET_SOK;
-
+    //ENETTRACE_ERR(ENETPHY_SOK,"dans=EnetPhyMdioDflt_ioctl =%x\r\n", cmd);
+    //ENETTRACE_INFO("dans=EnetPhyMdioDflt_ioctl---0\r\n");
     switch (cmd)
     {
         case ENET_PHY_IOCTL_GET_ID:
@@ -395,6 +397,8 @@ int32_t EnetPhyMdioDflt_ioctl(EnetPhy_Handle hPhy,
             status = EnetPhy_getId(hPhy, version);
             ENETTRACE_ERR_IF(status != ENETPHY_SOK, status,
                              "Port %u: Failed to get PHY id", portId);
+            //ENETTRACE_ERR(ENETPHY_SOK,"dans=EnetPhy_getId =%x =%x\r\n", version->oui, version->model);
+
         }
         break;
 
@@ -544,6 +548,6 @@ int32_t EnetPhyMdioDflt_ioctl(EnetPhy_Handle hPhy,
             break;
         }
     }
-
+    //ENETTRACE_INFO("dans=EnetPhyMdioDflt_ioctl---1\r\n");
     return status;
 }
diff --git a/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/core/enet.c b/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/core/enet.c
index 7491c910..fd01ea18 100644
--- a/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/core/enet.c
+++ b/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/core/enet.c
@@ -1310,7 +1310,7 @@ int32_t EnetMod_open(EnetMod_Handle hMod,
 
     /* open() function is mandatory */
     Enet_devAssert(hMod->open != NULL, "%s: Invalid open function", hMod->name);
-
+    //ENETTRACE_ERR(ENETPHY_SOK,"dans=EnetMod_open=%s\r\n",hMod->name);
     ENETTRACE_VERBOSE("%s: Open module", hMod->name);
 
     if (hMod->magic == ENET_NO_MAGIC)
@@ -1335,7 +1335,7 @@ int32_t EnetMod_open(EnetMod_Handle hMod,
         status = ENET_EALREADYOPEN;
         ENETTRACE_ERR(status, "%s: Module is already open", hMod->name);
     }
-
+    //ENETTRACE_ERR(ENETPHY_SOK,"dans=EnetMod_open end\r\n");
     return status;
 }
 
diff --git a/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/mod/cpsw_ale.c b/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/mod/cpsw_ale.c
index 05da5729..ca6f71ce 100644
--- a/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/mod/cpsw_ale.c
+++ b/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/mod/cpsw_ale.c
@@ -1165,7 +1165,7 @@ static Enet_IoctlValidate gCpswAle_ioctlValidate[] =
 void CpswAle_initCfg(CpswAle_Cfg *aleCfg)
 {
     uint32_t i;
-
+    //ENETTRACE_INFO("dans=CpswAle_initCfg\r\n");
     memset(aleCfg, 0, sizeof(*aleCfg));
     aleCfg->modeFlags = CPSW_ALE_CFG_MODULE_EN;
     aleCfg->policerGlobalCfg.policingEn   = TRUE;
diff --git a/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/mod/cpsw_macport.c b/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/mod/cpsw_macport.c
index cc56bd8b..fe087f31 100644
--- a/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/mod/cpsw_macport.c
+++ b/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/mod/cpsw_macport.c
@@ -2309,7 +2309,7 @@ static int32_t CpswMacPort_setSgmiiInterface(CSL_Xge_cpswRegs *regs,
      * other side of the fiber or wire (ie. to the remote system). The CPSGMII is
      * the link to the PHY.  The PHY auto-negotiates with the other side and
      * then the CPSGMII auto-negotiates with the PHY. */
-
+    //ENETTRACE_ERR(ENETPHY_SOK,"dans=CpswMacPort_setSgmiiInterface=%d\r\n",portNum);
     /* Confirm SERDES PLL is locked before configuring the port */
     if (linkCfg->speed != ENET_SPEED_10GBIT)
     {
@@ -2317,10 +2317,17 @@ static int32_t CpswMacPort_setSgmiiInterface(CSL_Xge_cpswRegs *regs,
         {
             status = ENET_EUNEXPECTED;
             ENETTRACE_ERR(status, "MAC %u: SERDES PLL is not locked", portId);
+            //ENETTRACE_ERR(ENET_SOK,"dans--CSL_SGMII_getSerdesPLLLockStatus ==%x",sgmiiRegs[portNum].STATUS_REG);
             Enet_devAssert(false);
         }
+        //else
+        //{
+        //    ENETTRACE_ERR(ENET_SOK,"dans--CSL_SGMII_getSerdesPLLLockStatus111 ==%x",sgmiiRegs[portNum].STATUS_REG);
+        //}
     }
 
+
+
     if (status == ENET_SOK)
     {
         status = CpswMacPort_configSgmii(sgmiiRegs, sgmiiMode, macPort, linkCfg);
@@ -2348,14 +2355,15 @@ static int32_t CpswMacPort_configSgmii(CSL_CpsgmiiRegs *sgmiiRegs,
     uint32_t portNum = ENET_MACPORT_NORM(macPort);
     uint32_t portId = ENET_MACPORT_ID(macPort);
     int32_t status = ENET_SOK;
-
+    //ENETTRACE_DBG("dans %u: CpswMacPort_configSgmii", portId);
+    //ENETTRACE_ERR(ENETPHY_SOK,"dans123=CpswMacPort_configSgmii =%d\r\n", portNum);
     ENETTRACE_VAR(portId);
     memset(&sgmiiAdvAbility, 0, sizeof(sgmiiAdvAbility));
 
     if (sgmiiMode == ENET_MAC_SGMIIMODE_FIBER_WITH_PHY)
     {
         ENETTRACE_DBG("MAC %u: Configuring SGMII in FIBER_WITH_PHY mode", portId);
-
+        ENETTRACE_ERR(ENETPHY_SOK,"dans123=ENET_MAC_SGMIIMODE_FIBER_WITH_PHY =%d\r\n", portNum);
         /* In fiber mode Advertise full-duplex only */
         sgmiiAdvAbility.duplexMode = CSL_SGMII_FULL_DUPLEX;
         sgmiiAdvAbility.sgmiiMode  = CSL_SGMII_MODE_FIBER;
@@ -2366,7 +2374,7 @@ static int32_t CpswMacPort_configSgmii(CSL_CpsgmiiRegs *sgmiiRegs,
     else if (sgmiiMode == ENET_MAC_SGMIIMODE_SGMII_WITH_PHY)
     {
         ENETTRACE_DBG("MAC %u: Configuring SGMII in SGMII_WITH_PHY mode", portId);
-
+        ENETTRACE_ERR(ENETPHY_SOK,"dans123=ENET_MAC_SGMIIMODE_SGMII_WITH_PHY =%d\r\n", portNum);
         /* Set highest speed when auto-negotiating with PHY. We don't need to configure
          * user provided speed/duplexity here as it is set in PHY and we auto-negotiate
          * with PHY.  For example, app wants to set 100Mbps full-duplex, it will be set
@@ -2386,7 +2394,7 @@ static int32_t CpswMacPort_configSgmii(CSL_CpsgmiiRegs *sgmiiRegs,
     else if (sgmiiMode == ENET_MAC_SGMIIMODE_SGMII_AUTONEG_MASTER)
     {
         ENETTRACE_DBG("MAC %u: Configure SGMII in SGMII_AUTONEG_MASTER mode", portId);
-
+        ENETTRACE_ERR(ENETPHY_SOK,"dans123=ENET_MAC_SGMIIMODE_SGMII_AUTONEG_MASTER =%d\r\n", portNum);
         /* For SGMII master, advertise full-duplex gigabit */
         sgmiiAdvAbility.linkSpeed  = CSL_SGMII_1000_MBPS;
         sgmiiAdvAbility.duplexMode = CSL_SGMII_FULL_DUPLEX;
@@ -2400,7 +2408,7 @@ static int32_t CpswMacPort_configSgmii(CSL_CpsgmiiRegs *sgmiiRegs,
     else if (sgmiiMode == ENET_MAC_SGMIIMODE_SGMII_AUTONEG_SLAVE)
     {
         ENETTRACE_DBG("MAC %u: Configure SGMII in SGMII_AUTONEG_SLAVE mode", portId);
-
+        ENETTRACE_ERR(ENETPHY_SOK,"dans123=ENET_MAC_SGMIIMODE_SGMII_AUTONEG_SLAVE =%d\r\n", portNum);
         /* To write 1 to tx_config_reg[0] bit, we pass empty ability structure */
         sgmiiAdvAbility.sgmiiMode  = CSL_SGMII_MODE_SGMII;
 
@@ -2411,7 +2419,7 @@ static int32_t CpswMacPort_configSgmii(CSL_CpsgmiiRegs *sgmiiRegs,
     else if (sgmiiMode == ENET_MAC_SGMIIMODE_SGMII_FORCEDLINK)
     {
         ENETTRACE_DBG("MAC %u: Configure SGMII in SGMII_FORCEDLINK mode", portId);
-
+        ENETTRACE_ERR(ENETPHY_SOK,"dans123=ENET_MAC_SGMIIMODE_SGMII_FORCEDLINK =%d\r\n", portNum);
         CpswMacPort_mapSgmiiLinkCfg(&sgmiiAdvAbility, linkCfg);
         sgmiiAdvAbility.bLinkUp   = 1U;
         sgmiiAdvAbility.sgmiiMode = CSL_SGMII_MODE_SGMII;
@@ -2436,6 +2444,7 @@ static int32_t CpswMacPort_configSgmii(CSL_CpsgmiiRegs *sgmiiRegs,
     {
         status = ENET_EINVALIDPARAMS;
         ENETTRACE_ERR(status, "MAC %u: Invalid SGMII mode config", portId);
+        ENETTRACE_ERR(ENETPHY_SOK,"dans123=nvalid SGMII mode config=%d\r\n", portNum);
     }
 
     return status;
diff --git a/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/mod/mdio.c b/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/mod/mdio.c
index 0b1b2095..624f94cc 100644
--- a/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/mod/mdio.c
+++ b/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/mod/mdio.c
@@ -180,6 +180,8 @@ void Mdio_initCfg(Mdio_Cfg *mdioCfg)
     mdioCfg->phyStatePollFreqHz = mdioCfg->mdioBusFreqHz;
     mdioCfg->c45EnMask          = ENET_MDIO_PHY_ADDR_MASK_NONE;
     mdioCfg->isMaster           = true;
+
+        //ENETTRACE_INFO("dans=Mdio_initCfg\r\n");
 }
 
 int32_t Mdio_open(EnetMod_Handle hMod,
@@ -195,7 +197,7 @@ int32_t Mdio_open(EnetMod_Handle hMod,
     uint32_t clkdiv;
     uint32_t ipgRatio;
     int32_t status = ENET_SOK;
-
+    //ENETTRACE_INFO("dans=Mdio_open\r\n");
     Enet_devAssert(cfgSize == sizeof(Mdio_Cfg),
                    "Invalid MDIO config params size %u (expected %u)",
                    cfgSize, sizeof(Mdio_Cfg));
diff --git a/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/per/cpsw.c b/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/per/cpsw.c
index 0a8895fa..d793ba0a 100644
--- a/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/per/cpsw.c
+++ b/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/per/cpsw.c
@@ -306,7 +306,7 @@ void Cpsw_initCfg(EnetPer_Handle hPer,
 {
     Cpsw_Cfg *cpswCfg = (Cpsw_Cfg *)cfg;
     uint32_t i;
-
+    //ENETTRACE_INFO("dans=Cpsw_initCfg\r\n");
     Enet_devAssert(cfgSize == sizeof(Cpsw_Cfg),
                    "Invalid CPSW peripheral config params size %u (expected %u)",
                    cfgSize, sizeof(Cpsw_Cfg));
@@ -365,7 +365,7 @@ int32_t Cpsw_open(EnetPer_Handle hPer,
     uintptr_t key;
     uint32_t i;
     int32_t status = ENET_SOK;
-
+    //ENETTRACE_INFO("dans=Cpsw_open\r\n");
     Enet_devAssert(cfgSize == sizeof(Cpsw_Cfg),
                    "Invalid CPSW peripheral config params size %u (expected %u)",
                    cfgSize, sizeof(Cpsw_Cfg));
@@ -724,7 +724,7 @@ int32_t Cpsw_ioctl(EnetPer_Handle hPer,
     Cpsw_Handle hCpsw = (Cpsw_Handle)hPer;
     uint32_t major;
     int32_t status = ENET_SOK;
-
+    //ENETTRACE_INFO("dans=Cpsw_ioctl\r\n");
     if (ENET_IOCTL_GET_TYPE(cmd) != ENET_IOCTL_TYPE_PUBLIC)
     {
         status = ENET_EINVALIDPARAMS;
@@ -740,24 +740,28 @@ int32_t Cpsw_ioctl(EnetPer_Handle hPer,
             case ENET_IOCTL_PER_BASE:
             {
                 status = Cpsw_ioctlInternal(hPer, cmd, prms);
+                //ENETTRACE_INFO("dans=ENET_IOCTL_PER_BASE\r\n");
             }
             break;
 
             case ENET_IOCTL_FDB_BASE:
             {
                 status = EnetMod_ioctl(hCpsw->hAle, cmd, prms);
+                //ENETTRACE_INFO("dans=ENET_IOCTL_FDB_BASE\r\n");
             }
             break;
 
             case ENET_IOCTL_TIMESYNC_BASE:
             {
                 status = EnetMod_ioctl(hCpsw->hCpts, cmd, prms);
+                //ENETTRACE_INFO("dans=ENET_IOCTL_TIMESYNC_BASE\r\n");
             }
             break;
 
             case ENET_IOCTL_HOSTPORT_BASE:
             {
                 status = EnetMod_ioctl(hCpsw->hHostPort, cmd, prms);
+                //ENETTRACE_INFO("dans=ENET_IOCTL_HOSTPORT_BASE\r\n");
             }
             break;
 
@@ -770,6 +774,7 @@ int32_t Cpsw_ioctl(EnetPer_Handle hPer,
                 if (ENET_FEAT_IS_EN(hPer->features, CPSW_FEATURE_EST))
                 {
                     status = Cpsw_ioctlEst(hPer, cmd, prms);
+                    //ENETTRACE_INFO("dans=ENET_IOCTL_TAS_BASE\r\n");
                 }
                 else
                 {
@@ -787,7 +792,7 @@ int32_t Cpsw_ioctl(EnetPer_Handle hPer,
                  * MAC port IOCTL input args have macPort as their first member */
                 EnetMacPort_GenericInArgs *inArgs = (EnetMacPort_GenericInArgs *)prms->inArgs;
                 uint32_t portNum = ENET_MACPORT_NORM(inArgs->macPort);
-
+                //ENETTRACE_INFO("dans=ENET_IOCTL_MACPORT_BASE\r\n");
                 if (portNum < EnetSoc_getMacPortMax(hPer->enetType, hPer->instId))
                 {
                     status = EnetMod_ioctl(hCpsw->hMacPort[portNum], cmd, prms);
@@ -803,12 +808,14 @@ int32_t Cpsw_ioctl(EnetPer_Handle hPer,
             case ENET_IOCTL_MDIO_BASE:
             {
                 status = EnetMod_ioctl(hCpsw->hMdio, cmd, prms);
+                //ENETTRACE_INFO("dans=ENET_IOCTL_MDIO_BASE\r\n");
             }
             break;
 
             case ENET_IOCTL_STATS_BASE:
             {
                 status = EnetMod_ioctl(hCpsw->hStats, cmd, prms);
+                //ENETTRACE_INFO("dans=ENET_IOCTL_STATS_BASE\r\n");
             }
             break;
 
@@ -823,6 +830,7 @@ int32_t Cpsw_ioctl(EnetPer_Handle hPer,
                 if (hPhy != NULL)
                 {
                     status = EnetPhyMdioDflt_ioctl(hCpsw->hPhy[portNum], cmd, prms);
+                    //ENETTRACE_INFO("dans=ENET_IOCTL_PHY_BASE\r\n");
                 }
                 else
                 {
@@ -835,6 +843,7 @@ int32_t Cpsw_ioctl(EnetPer_Handle hPer,
             case ENET_IOCTL_RM_BASE:
             {
                 status = EnetMod_ioctl(hCpsw->hRm, cmd, prms);
+                //ENETTRACE_INFO("dans=ENET_IOCTL_RM_BASE\r\n");
             }
             break;
 
@@ -1231,14 +1240,14 @@ static int32_t Cpsw_ioctlInternal(EnetPer_Handle hPer,
         ENETTRACE_ERR_IF(status != ENET_SOK, status, "IOCTL 0x%08x params are not valid", cmd);
     }
 #endif
-
+    //ENETTRACE_INFO("dans=Cpsw_ioctlInternal\r\n");
     switch (cmd)
     {
         case ENET_PER_IOCTL_GET_VERSION:
         {
             Enet_Version *version = (Enet_Version *)prms->outArgs;
             CSL_CPSW_VERSION ver;
-
+            //ENETTRACE_INFO("dans=ENET_PER_IOCTL_GET_VERSION\r\n");
             CSL_CPSW_getCpswVersionInfo(regs, &ver);
             version->maj = ver.majorVer;
             version->min = ver.minorVer;
@@ -1246,12 +1255,14 @@ static int32_t Cpsw_ioctlInternal(EnetPer_Handle hPer,
             version->id  = ver.id;
             version->other1 = ENET_VERSION_NONE;
             version->other2 = ENET_VERSION_NONE;
+            //ENETTRACE_ERR(ENETPHY_SOK,"dans=ENET_PER_IOCTL_GET_VERSION =%d\r\n", version->maj);
         }
         break;
 
         case ENET_PER_IOCTL_PRINT_REGS:
         {
             status = Cpsw_printRegisters(hCpsw);
+            //ENETTRACE_INFO("dans=ENET_PER_IOCTL_PRINT_REGS\r\n");
         }
         break;
 
@@ -1263,7 +1274,8 @@ static int32_t Cpsw_ioctlInternal(EnetPer_Handle hPer,
             const EnetPhy_Cfg *phyCfg = &portLinkCfg->phyCfg;
             const EnetMacPort_Interface *mii = &portLinkCfg->mii;
             const EnetMacPort_LinkCfg *linkCfg = &portLinkCfg->linkCfg;
-
+            //ENETTRACE_INFO("dans=ENET_PER_IOCTL_OPEN_PORT_LINK\r\n");
+             //   ENETTRACE_ERR(ENETPHY_SOK,"dans=ENET_PER_IOCTL_OPEN_PORT_LINK =%d\r\n", phyCfg->phyAddr);
             if (macCfg->rxMtu > hCpsw->maxPerPrioMtu)
             {
                 /* Host port and MAC port MTU should not be greater than largest of the port
@@ -1287,7 +1299,7 @@ static int32_t Cpsw_ioctlInternal(EnetPer_Handle hPer,
         case ENET_PER_IOCTL_CLOSE_PORT_LINK:
         {
             Enet_MacPort macPort = *(Enet_MacPort *)prms->inArgs;
-
+            //ENETTRACE_INFO("dans=ENET_PER_IOCTL_CLOSE_PORT_LINK\r\n");
             Cpsw_closePortLink(hCpsw, macPort);
         }
         break;
@@ -1297,7 +1309,7 @@ static int32_t Cpsw_ioctlInternal(EnetPer_Handle hPer,
             Enet_MacPort macPort = *(Enet_MacPort *)prms->inArgs;
             bool *linkUp = (bool *)prms->outArgs;
             uint32_t portNum = ENET_MACPORT_NORM(macPort);
-
+            //ENETTRACE_INFO("dans=ENET_PER_IOCTL_IS_PORT_LINK_UP\r\n");
             *linkUp = hCpsw->portLinkState[portNum].isLinkUp;
         }
         break;
@@ -1306,7 +1318,7 @@ static int32_t Cpsw_ioctlInternal(EnetPer_Handle hPer,
         {
             Enet_MacPort macPort = *(Enet_MacPort *)prms->inArgs;
             EnetMacPort_LinkCfg *linkCfg = (EnetMacPort_LinkCfg *)prms->outArgs;
-
+            //ENETTRACE_INFO("dans=ENET_PER_IOCTL_GET_PORT_LINK_CFG\r\n");
             status = Cpsw_getPortLinkCfg(hCpsw, macPort, linkCfg);
             ENETTRACE_ERR_IF(status != ENET_SOK, status,
                              "Port %u: Failed to get link config", ENET_MACPORT_ID(macPort));
@@ -1319,7 +1331,7 @@ static int32_t Cpsw_ioctlInternal(EnetPer_Handle hPer,
             EnetPer_AttachCoreOutArgs *outArgs = (EnetPer_AttachCoreOutArgs *)prms->outArgs;
             Enet_IoctlPrms rmPrms;
             uint32_t i;
-
+            //ENETTRACE_INFO("dans=ENET_PER_IOCTL_ATTACH_CORE\r\n");
             ENET_IOCTL_SET_INOUT_ARGS(&rmPrms, &coreId, &outArgs->coreKey);
 
             status = EnetMod_ioctl(hCpsw->hRm, ENET_RM_IOCTL_ATTACH, &rmPrms);
@@ -1904,7 +1916,7 @@ static int32_t Cpsw_openPortLinkWithPhy(Cpsw_Handle hCpsw,
     CpswMacPort_ModCfg macModCfg;
     uint32_t macPortCaps;
     int32_t status;
-
+    //ENETTRACE_ERR(ENETPHY_SOK,"dans=Cpsw_openPortLinkWithPhy =%d\r\n", phyCfg->phyAddr);
     ENETTRACE_VAR(portId);
     /* Enet module takes a single config structure, which in CPSW MAC port case is
      * EnetMacPort_ModCfg. This structure contains the initial MAC specific configuration
@@ -1916,10 +1928,11 @@ static int32_t Cpsw_openPortLinkWithPhy(Cpsw_Handle hCpsw,
     /* Open MAC port */
     status = EnetMod_open(hMacPort, hPer->enetType, hPer->instId, &macModCfg, sizeof(macModCfg));
     ENETTRACE_ERR_IF(status != ENET_SOK, status, "Port %u: Failed to open MAC", portId);
-
+    //ENETTRACE_ERR(ENETPHY_SOK,"dans=Cpsw_openPortLinkWithPhy1\r\n");
     /* Open PHY */
     if (status == ENET_SOK)
     {
+        //ENETTRACE_ERR(ENETPHY_SOK,"dans=Cpsw_openPortLinkWithPhy2\r\n");
         /* Convert MII and link configuration from Enet to ENETPHY types */
         phyMii = EnetUtils_macToPhyMii(mii);
         phyLinkCfg.speed = (EnetPhy_Speed)linkCfg->speed;
@@ -1937,7 +1950,7 @@ static int32_t Cpsw_openPortLinkWithPhy(Cpsw_Handle hCpsw,
             CpswMacPort_close(hMacPort);
         }
     }
-
+    //ENETTRACE_ERR(ENETPHY_SOK,"dans=Cpsw_openPortLinkWithPhy3\r\n");
     return status;
 }
 
@@ -2078,7 +2091,8 @@ static int32_t Cpsw_openPortLink(Cpsw_Handle hCpsw,
     uint32_t pollEnMask = hCpsw->mdioLinkIntCtx.pollEnableMask;
     uint32_t phyAddr = phyCfg->phyAddr;
     int32_t status = ENET_SOK;
-
+    //ENETTRACE_INFO("dans=Cpsw_openPortLink\r\n");
+    //ENETTRACE_ERR(ENETPHY_SOK,"dans=Cpsw_openPortLink =%d\r\n", phyCfg->phyAddr);
     ENETTRACE_VAR(portId);
     if ((portNum >= EnetSoc_getMacPortMax(hPer->enetType, hPer->instId)) ||
         EnetMod_isOpen(hMacPort) ||
diff --git a/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/phy/enetphy.c b/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/phy/enetphy.c
index 49335794..b3cc232d 100644
--- a/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/phy/enetphy.c
+++ b/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/phy/enetphy.c
@@ -52,7 +52,7 @@
 #include <ti/drv/enet/include/phy/enetphy.h>
 #include "enetphy_priv.h"
 #include "generic_phy.h"
-
+#include "RTL9010_priv.h"
 /* ========================================================================== */
 /*                           Macros & Typedefs                                */
 /* ========================================================================== */
@@ -182,13 +182,14 @@ extern EnetPhy_Drv gEnetPhyDrvGeneric;
 extern EnetPhy_Drv gEnetPhyDrvDp83822;
 extern EnetPhy_Drv gEnetPhyDrvDp83867;
 extern EnetPhy_Drv gEnetPhyDrvVsc8514;
-
+extern EnetPhy_Drv gEnetPhyDrvRTL9010;
 /*! \brief All the registered PHY specific drivers. */
 static EnetPhyDrv_Handle gEnetPhyDrvs[] =
 {
     &gEnetPhyDrvVsc8514,   /* VSC8514 */
     &gEnetPhyDrvDp83822,   /* DP83822 */
     &gEnetPhyDrvDp83867,   /* DP83867 */
+    &gEnetPhyDrvRTL9010,
     &gEnetPhyDrvGeneric,   /* Generic PHY - must be last */
 };
 
@@ -229,7 +230,7 @@ static char gEnetPhyModeBuf[ENETPHY_MODE_BUF_LEN];
 void EnetPhy_initCfg(EnetPhy_Cfg *phyCfg)
 {
     memset(phyCfg, 0, sizeof(*phyCfg));
-
+    ENETTRACE_ERR(ENETPHY_SOK,"dans=EnetPhy_initCfg =%d\r\n", phyCfg->phyAddr);
     phyCfg->phyAddr = ENETPHY_INVALID_PHYADDR;
     phyCfg->nwayCaps = ENETPHY_LINK_CAP_ALL;
     phyCfg->mdixEn = true;
@@ -274,7 +275,7 @@ EnetPhy_Handle EnetPhy_open(const EnetPhy_Cfg *phyCfg,
     bool manualMode = false;
     bool alive;
     int32_t status = ENETPHY_SOK;
-
+    ENETTRACE_ERR(ENETPHY_SOK,"dans=EnetPhy_open =%d\r\n", phyCfg->phyAddr);
     if (hPhy == NULL)
     {
         status = ENETPHY_EALLOC;
@@ -326,7 +327,7 @@ EnetPhy_Handle EnetPhy_open(const EnetPhy_Cfg *phyCfg,
             {
                 EnetPhy_setNextState(hPhy, ENETPHY_FSM_STATE_FOUND);
             }
-
+            ENETTRACE_ERR(ENETPHY_SOK,"dans=EnetPhy_open111\r\n");
             status = EnetPhy_bindDriver(hPhy);
         }
         else
@@ -393,58 +394,69 @@ EnetPhy_LinkStatus EnetPhy_tick(EnetPhy_Handle hPhy)
     switch (state->fsmState)
     {
         case ENETPHY_FSM_STATE_INIT:
-            ENETTRACE_VERBOSE("PHY %u: INIT", hPhy->addr);
+            //ENETTRACE_VERBOSE("PHY %u: INIT", hPhy->addr);
+           // ENETTRACE_ERR(ENETPHY_SOK,"dans=EnetPhy_initState =%d\r\n", hPhy->addr);
             EnetPhy_initState(hPhy);
             break;
 
         case ENETPHY_FSM_STATE_FINDING:
-            ENETTRACE_VERBOSE("PHY %u: FINDING (rem ticks %u)",
-                              hPhy->addr, state->timeout);
+            // ENETTRACE_VERBOSE("PHY %u: FINDING (rem ticks %u)",
+            //                   hPhy->addr, state->timeout);
+            //ENETTRACE_ERR(ENETPHY_SOK,"dans=EnetPhy_findingState =%d\r\n", hPhy->addr);
             EnetPhy_findingState(hPhy);
             break;
 
         case ENETPHY_FSM_STATE_FOUND:
-            ENETTRACE_VERBOSE("PHY %u: FOUND", hPhy->addr);
+            //ENETTRACE_VERBOSE("PHY %u: FOUND", hPhy->addr);
+            //ENETTRACE_ERR(ENETPHY_SOK,"dans=EnetPhy_foundState =%d\r\n", hPhy->addr);
             EnetPhy_foundState(hPhy);
             break;
 
         case ENETPHY_FSM_STATE_RESET_WAIT:
-            ENETTRACE_VERBOSE("PHY %u: RESET_WAIT", hPhy->addr);
+            //ENETTRACE_VERBOSE("PHY %u: RESET_WAIT", hPhy->addr);
+            ENETTRACE_ERR(ENETPHY_SOK,"dans=EnetPhy_resetWaitState =%d\r\n", hPhy->addr);
             EnetPhy_resetWaitState(hPhy);
             break;
 
         case ENETPHY_FSM_STATE_ENABLE:
-            ENETTRACE_VERBOSE("PHY %u: ENABLE", hPhy->addr);
+            //ENETTRACE_VERBOSE("PHY %u: ENABLE", hPhy->addr);
+            //ENETTRACE_ERR(ENETPHY_SOK,"dans=EnetPhy_enableState =%d\r\n", hPhy->addr);
             EnetPhy_enableState(hPhy);
             break;
 
         case ENETPHY_FSM_STATE_NWAY_START:
-            ENETTRACE_VERBOSE("PHY %u: NWAY_START (rem ticks %u)", hPhy->addr, state->timeout);
+            //ENETTRACE_VERBOSE("PHY %u: NWAY_START (rem ticks %u)", hPhy->addr, state->timeout);
+            //ENETTRACE_ERR(ENETPHY_SOK,"dans=EnetPhy_nwayStartState =%d\r\n", hPhy->addr);
             EnetPhy_nwayStartState(hPhy);
             break;
 
         case ENETPHY_FSM_STATE_NWAY_WAIT:
-            ENETTRACE_VERBOSE("PHY %u: NWAY_WAIT (rem ticks %u)", hPhy->addr, state->timeout);
+            //ENETTRACE_VERBOSE("PHY %u: NWAY_WAIT (rem ticks %u)", hPhy->addr, state->timeout);
+            //ENETTRACE_ERR(ENETPHY_SOK,"dans=EnetPhy_nwayWaitState =%d\r\n", hPhy->addr);
             EnetPhy_nwayWaitState(hPhy);
             break;
 
         case ENETPHY_FSM_STATE_LINK_WAIT:
-            ENETTRACE_VERBOSE("PHY %u: LINK_WAIT (rem ticks %u)", hPhy->addr, state->timeout);
+            //ENETTRACE_VERBOSE("PHY %u: LINK_WAIT (rem ticks %u)", hPhy->addr, state->timeout);
+            //ENETTRACE_ERR(ENETPHY_SOK,"dans=EnetPhy_linkWaitState =%d\r\n", hPhy->addr);
             EnetPhy_linkWaitState(hPhy);
             break;
 
         case ENETPHY_FSM_STATE_LINKED:
-            ENETTRACE_VERBOSE("PHY %u: LINKED", hPhy->addr);
+            //ENETTRACE_VERBOSE("PHY %u: LINKED", hPhy->addr);
+            //ENETTRACE_ERR(ENETPHY_SOK,"dans=EnetPhy_linkedState =%d\r\n", hPhy->addr);
             EnetPhy_linkedState(hPhy);
             break;
 
         case ENETPHY_FSM_STATE_LOOPBACK:
-            ENETTRACE_VERBOSE("PHY %u: LOOPBACK", hPhy->addr);
+            //ENETTRACE_VERBOSE("PHY %u: LOOPBACK", hPhy->addr);
+            //ENETTRACE_ERR(ENETPHY_SOK,"dans=EnetPhy_loopbackState =%d\r\n", hPhy->addr);
             EnetPhy_loopbackState(hPhy);
             break;
 
         default:
-            ENETTRACE_VERBOSE("PHY %u: DEFAULT", hPhy->addr);
+            //ENETTRACE_VERBOSE("PHY %u: DEFAULT", hPhy->addr);
+            //ENETTRACE_ERR(ENETPHY_SOK,"dans=EnetPhy_defaultState =%d\r\n", hPhy->addr);
             EnetPhy_defaultState(hPhy);
             break;
     }
@@ -566,6 +578,7 @@ int32_t EnetPhy_getId(EnetPhy_Handle hPhy,
         version->revision = (id2 & PHYIDR2_VREV_MASK) >> PHYIDR2_VREV_OFFSET;
     }
 
+    ENETTRACE_ERR(ENETPHY_SOK,"dans=EnetPhy_getId0000 =%x =%x\r\n", version->oui, version->model);
     return status;
 }
 
@@ -982,7 +995,7 @@ static void EnetPhy_findingState(EnetPhy_Handle hPhy)
     {
         /* PHY found */
         ENETTRACE_DBG("PHY %u: PHY has been found", phyAddr);
-
+        ENETTRACE_ERR(ENETPHY_SOK,"dans=EnetPhy_findingState1111\r\n");
         status = EnetPhy_bindDriver(hPhy);
         if (status == ENETPHY_SOK)
         {
@@ -1148,13 +1161,13 @@ static void EnetPhy_enableState(EnetPhy_Handle hPhy)
     }
     else if (state->isNwayCapable && state->enableNway)
     {
-        ENETTRACE_DBG("PHY %u: setup NWAY", hPhy->addr);
-        EnetPhy_setupNway(hPhy);
-        EnetPhy_setNextState(hPhy, ENETPHY_FSM_STATE_NWAY_START);
-    }
-    else
-    {
-        ENETTRACE_DBG("PHY %u: manual setup", hPhy->addr);
+    //     ENETTRACE_ERR("PHY %u: setup NWAY\r\n", hPhy->addr);
+    //     EnetPhy_setupNway(hPhy);
+    //     EnetPhy_setNextState(hPhy, ENETPHY_FSM_STATE_NWAY_START);
+    // }
+    // else
+    // {
+        //ENETTRACE_ERR("PHY %u: manual setup\r\n", hPhy->addr);
         EnetPhy_setupManual(hPhy, false);
         EnetPhy_setNextState(hPhy, ENETPHY_FSM_STATE_LINK_WAIT);
     }
@@ -1162,67 +1175,68 @@ static void EnetPhy_enableState(EnetPhy_Handle hPhy)
 
 static void EnetPhy_setupNway(EnetPhy_Handle hPhy)
 {
-    EnetPhy_State *state = &hPhy->state;
-    uint16_t nwayAdvertise;
-    uint16_t nway1000Advertise = 0U;
-
-    ENETTRACE_DBG("PHY %u: NWAY advertising: %s",
-                  hPhy->addr, EnetPhy_getCapsString(state->linkCaps));
-
-    ENETTRACE_DBG("PHY %u: config is %sneeded",
-                  hPhy->addr, state->needsNwayCfg ? "" : "not ");
-
-    if (state->needsNwayCfg)
-    {
-        nwayAdvertise = ANAR_802P3;
-        if ((state->linkCaps & ENETPHY_LINK_CAP_FD100) != 0U)
-        {
-            nwayAdvertise |= ANAR_100FD;
-        }
-
-        if ((state->linkCaps & ENETPHY_LINK_CAP_HD100) != 0U)
-        {
-            nwayAdvertise |= ANAR_100HD;
-        }
-
-        if ((state->linkCaps & ENETPHY_LINK_CAP_FD10) != 0U)
-        {
-            nwayAdvertise |= ANAR_10FD;
-        }
-
-        if ((state->linkCaps & ENETPHY_LINK_CAP_HD10) != 0U)
-        {
-            nwayAdvertise |= ANAR_10HD;
-        }
-
-        if ((state->linkCaps & ENETPHY_LINK_CAP_FD1000) != 0U)
-        {
-            nway1000Advertise |= GIGCR_1000FD;
-        }
-
-        if ((state->linkCaps & ENETPHY_LINK_CAP_HD1000) != 0U)
-        {
-            nway1000Advertise |= GIGCR_1000HD;
-        }
-
-        EnetPhy_rmwReg(hPhy, PHY_ANAR, ANAR_100 | ANAR_10, nwayAdvertise);
-
-        if ((state->phyLinkCaps & ENETPHY_LINK_CAP_1000) != 0U)
-        {
-            EnetPhy_rmwReg(hPhy, PHY_GIGCR, GIGCR_1000, nway1000Advertise);
-        }
-
-        state->needsNwayCfg = false;
-    }
-
-    /* Restart auto-negotiation */
-    ENETTRACE_DBG("PHY %u: restart autonegotiation", hPhy->addr);
-    EnetPhy_rmwReg(hPhy, PHY_BMCR, BMCR_ANEN, BMCR_ANEN);
-
-    /* TODO: is MII_ENETPHY_FD needed for auto-negotiation? */
-    EnetPhy_rmwReg(hPhy, PHY_BMCR,
-                   BMCR_ANRESTART | BMCR_FD,
-                   BMCR_ANRESTART | BMCR_FD);
+    // EnetPhy_State *state = &hPhy->state;
+    // uint16_t nwayAdvertise;
+    // uint16_t nway1000Advertise = 0U;
+
+    // ENETTRACE_ERR("PHY %u: NWAY advertising: %s\r\n",
+    //               hPhy->addr, EnetPhy_getCapsString(state->linkCaps));
+
+    // ENETTRACE_ERR("PHY %u: config is %sneeded\r\n",
+    //               hPhy->addr, state->needsNwayCfg ? "" : "not ");
+
+    // if (state->needsNwayCfg)
+    // {
+    //     nwayAdvertise = ANAR_802P3;
+    //     if ((state->linkCaps & ENETPHY_LINK_CAP_FD100) != 0U)
+    //     {
+    //         nwayAdvertise |= ANAR_100FD;
+    //     }
+
+    //     if ((state->linkCaps & ENETPHY_LINK_CAP_HD100) != 0U)
+    //     {
+    //         nwayAdvertise |= ANAR_100HD;
+    //     }
+
+    //     if ((state->linkCaps & ENETPHY_LINK_CAP_FD10) != 0U)
+    //     {
+    //         nwayAdvertise |= ANAR_10FD;
+    //     }
+
+    //     if ((state->linkCaps & ENETPHY_LINK_CAP_HD10) != 0U)
+    //     {
+    //         nwayAdvertise |= ANAR_10HD;
+    //     }
+
+    //     if ((state->linkCaps & ENETPHY_LINK_CAP_FD1000) != 0U)
+    //     {
+    //         nway1000Advertise |= GIGCR_1000FD;
+    //     }
+
+    //     if ((state->linkCaps & ENETPHY_LINK_CAP_HD1000) != 0U)
+    //     {
+    //         nway1000Advertise |= GIGCR_1000HD;
+    //     }
+
+    //     // EnetPhy_rmwReg(hPhy, PHY_ANAR, ANAR_100 | ANAR_10, nwayAdvertise);
+
+    //     // if ((state->phyLinkCaps & ENETPHY_LINK_CAP_1000) != 0U)
+    //     // {
+    //     //     EnetPhy_rmwReg(hPhy, PHY_GIGCR, GIGCR_1000, nway1000Advertise);
+    //     // }
+
+    //     nwayAdvertise |= ANAR_100FD;
+    // //     state->needsNwayCfg = false;
+    // }
+
+    // /* Restart auto-negotiation */
+    // ENETTRACE_ERR("PHY %u: restart autonegotiation\r\n", hPhy->addr);
+    // EnetPhy_rmwReg(hPhy, PHY_BMCR, BMCR_ANEN, BMCR_ANEN);
+
+    // /* TODO: is MII_ENETPHY_FD needed for auto-negotiation? */
+    // EnetPhy_rmwReg(hPhy, PHY_BMCR,
+    //                BMCR_ANRESTART | BMCR_FD,
+    //                BMCR_ANRESTART | BMCR_FD);
 }
 
 static void EnetPhy_setupManual(EnetPhy_Handle hPhy,
@@ -1468,46 +1482,47 @@ static bool EnetPhy_isNwayCapable(EnetPhy_Handle hPhy)
 static uint32_t EnetPhy_getLocalCaps(EnetPhy_Handle hPhy)
 {
     uint32_t caps = 0U;
-    uint16_t val  = 0U;
+    //uint16_t val  = 0U;
 
     /* Get 10/100 Mbps capabilities */
-    EnetPhy_readReg(hPhy, PHY_BMSR, &val);
-    if ((val & BMSR_100FD) != 0U)
-    {
-        caps |= ENETPHY_LINK_CAP_FD100;
-    }
-
-    if ((val & BMSR_100HD) != 0U)
-    {
-        caps |= ENETPHY_LINK_CAP_HD100;
-    }
-
-    if ((val & BMSR_10FD) != 0U)
-    {
-        caps |= ENETPHY_LINK_CAP_FD10;
-    }
-
-    if ((val & BMSR_10HD) != 0U)
-    {
-        caps |= ENETPHY_LINK_CAP_HD10;
-    }
-
-    /* Get extended (1 Gbps) capabilities if supported */
-    if ((val & BMSR_GIGEXTSTS) != 0U)
-    {
-        EnetPhy_readReg(hPhy, PHY_GIGESR, &val);
-
-        if ((val & GIGESR_1000FD) != 0U)
-        {
-            caps |= ENETPHY_LINK_CAP_FD1000;
-        }
-
-        if ((val & GIGESR_1000HD) != 0U)
-        {
-            caps |= ENETPHY_LINK_CAP_HD1000;
-        }
-    }
-
+    //EnetPhy_readReg(hPhy, PHY_BMSR, &val);
+    // EnetPhy_readReg(hPhy, PHY_BMCR, &val);
+    // if ((val & BMSR_100FD) != 0U)
+    // {
+    //     caps |= ENETPHY_LINK_CAP_FD100;
+    // }
+
+    // if ((val & BMSR_100HD) != 0U)
+    // {
+    //     caps |= ENETPHY_LINK_CAP_HD100;
+    // }
+
+    // if ((val & BMSR_10FD) != 0U)
+    // {
+    //     caps |= ENETPHY_LINK_CAP_FD10;
+    // }
+
+    // if ((val & BMSR_10HD) != 0U)
+    // {
+    //     caps |= ENETPHY_LINK_CAP_HD10;
+    // }
+
+    // /* Get extended (1 Gbps) capabilities if supported */
+    // if ((val & BMSR_GIGEXTSTS) != 0U)
+    // {
+    //     EnetPhy_readReg(hPhy, PHY_GIGESR, &val);
+
+    //     if ((val & GIGESR_1000FD) != 0U)
+    //     {
+    //         caps |= ENETPHY_LINK_CAP_FD1000;
+    //     }
+
+    //     if ((val & GIGESR_1000HD) != 0U)
+    //     {
+    //         caps |= ENETPHY_LINK_CAP_HD1000;
+    //     }
+    // }
+    caps |= ENETPHY_LINK_CAP_FD1000;
     return caps;
 }
 
@@ -1578,33 +1593,34 @@ static uint32_t EnetPhy_findCommon1000Caps(EnetPhy_Handle hPhy)
 {
     uint32_t localCaps = 0U;
     uint32_t partnerCaps = 0U;
-    uint16_t val;
-
-    /* Get local device capabilities */
-    EnetPhy_readReg(hPhy, PHY_GIGCR, &val);
+    //uint16_t val;
 
-    if ((val & GIGCR_1000FD) != 0U)
-    {
-        localCaps |= ENETPHY_LINK_CAP_FD1000;
-    }
+    // /* Get local device capabilities */
+    // EnetPhy_readReg(hPhy, PHY_GIGCR, &val);
 
-    if ((val & GIGCR_1000HD) != 0U)
-    {
-        localCaps |= ENETPHY_LINK_CAP_HD1000;
-    }
+    // if ((val & GIGCR_1000FD) != 0U)
+    // {
+    //     localCaps |= ENETPHY_LINK_CAP_FD1000;
+    // }
 
+    // if ((val & GIGCR_1000HD) != 0U)
+    // {
+    //     localCaps |= ENETPHY_LINK_CAP_HD1000;
+    // }
+    localCaps |= ENETPHY_LINK_CAP_FD1000;
     /* Get link partner capabilities */
-    EnetPhy_readReg(hPhy, PHY_GIGSR, &val);
+    // EnetPhy_readReg(hPhy, PHY_GIGSR, &val);
 
-    if ((val & GIGSR_1000FD) != 0U)
-    {
-        partnerCaps |= ENETPHY_LINK_CAP_FD1000;
-    }
+    // if ((val & GIGSR_1000FD) != 0U)
+    // {
+    //     partnerCaps |= ENETPHY_LINK_CAP_FD1000;
+    // }
 
-    if ((val & GIGSR_1000FD) != 0U)
-    {
-        partnerCaps |= ENETPHY_LINK_CAP_HD1000;
-    }
+    // if ((val & GIGSR_1000FD) != 0U)
+    // {
+    //     partnerCaps |= ENETPHY_LINK_CAP_HD1000;
+    // }
+    partnerCaps |= ENETPHY_LINK_CAP_FD1000;
 
     ENETTRACE_DBG("PHY %u: local caps: %s",
                   hPhy->addr, EnetPhy_getCapsString(localCaps));
@@ -1619,17 +1635,18 @@ static uint32_t EnetPhy_findCommon1000Caps(EnetPhy_Handle hPhy)
 static uint32_t EnetPhy_findCommonNwayCaps(EnetPhy_Handle hPhy)
 {
     EnetPhy_State *state = &hPhy->state;
-    uint32_t nwayCaps;
+    uint32_t nwayCaps = 0;
     int32_t status = ENET_SOK;
 
     ENETTRACE_VAR(status);
 
-    nwayCaps = EnetPhy_findCommonCaps(hPhy);
+    //nwayCaps = EnetPhy_findCommonCaps(hPhy);
 
     /* Find common gigabit capabilities if supported by PHY */
     if ((state->phyLinkCaps & ENETPHY_LINK_CAP_1000) != 0U)
     {
         nwayCaps |= EnetPhy_findCommon1000Caps(hPhy);
+        ENETTRACE_ERR(ENET_SOK, "dans---PHY %u:", hPhy->addr);
     }
 
     ENETTRACE_DBG("PHY %u: common caps: %s",
@@ -1671,6 +1688,7 @@ static bool EnetPhy_isPhyLinked(EnetPhy_Handle hPhy)
     {
         /* Alternatively, BMSR[2] Link Status bit can be checked */
         status = hMdio->readC22(phyGroup, phyAddr, PHY_BMSR, &val, hPhy->mdioArgs);
+        ENETTRACE_ERR(ENETPHY_SOK, "daANS--PHY %u: Vl==%u:", hPhy->addr,val);
         ENETTRACE_ERR_IF(status != ENETPHY_SOK, status,
                          "PHY %u: Failed to read reg %u", phyAddr, PHY_BMSR);
         if ((status == ENETPHY_SOK) &&
diff --git a/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/phy/makefile b/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/phy/makefile
index f4c3b723..85616c61 100644
--- a/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/phy/makefile
+++ b/pdk_j784s4_09_01_00_22/packages/ti/drv/enet/src/phy/makefile
@@ -19,7 +19,7 @@ INCLUDE_INTERNAL_INTERFACES =
 
 # Common source files and CFLAGS across all platforms and cores
 SRCS_COMMON += enetphy.c generic_phy.c
-SRCS_COMMON += dp83867.c dp83822.c vsc8514.c
+SRCS_COMMON += dp83867.c dp83822.c vsc8514.c RTL9010.c
 
 PACKAGE_SRCS_COMMON = $(SRCDIR)
 CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) $(ENET_CFLAGS)
diff --git a/sdk_builder/tools_path.mak b/sdk_builder/tools_path.mak
index 89f775b9..d9b16077 100755
--- a/sdk_builder/tools_path.mak
+++ b/sdk_builder/tools_path.mak
@@ -1,7 +1,7 @@
 PSDK_PATH ?= $(abspath ..)
 
 # Compilers
-PSDK_TOOLS_PATH ?= $(HOME)/ti
+PSDK_TOOLS_PATH ?= /home/zdx/ti
 TIARMCGT_LLVM_ROOT ?= $(PSDK_TOOLS_PATH)/ti-cgt-armllvm_3.2.0.LTS
 CGT7X_ROOT ?= $(PSDK_TOOLS_PATH)/ti-cgt-c7000_3.1.0.LTS
 CGT6X_ROOT ?= $(PSDK_TOOLS_PATH)/ti-cgt-c6000_8.3.7
@@ -67,8 +67,8 @@ endif
 
 LINUX_FS_PATH ?= $(PSDK_PATH)/targetfs/
 LINUX_FS_BOOT_PATH ?= $(PSDK_PATH)/bootfs/
-LINUX_SD_FS_ROOT_PATH ?= /media/$(USER)/rootfs
-LINUX_SD_FS_BOOT_PATH ?= /media/$(USER)/BOOT
+LINUX_SD_FS_ROOT_PATH ?= /media/zdx/root
+LINUX_SD_FS_BOOT_PATH ?= /media/zdx/boot
 
 ifeq ($(SOC),j721e)
   export PSDK_LINUX_PATH ?= $(HOME)/ti-processor-sdk-linux-adas-j721e-evm-09_01_00_06
diff --git a/vision_apps/platform/j784s4/rtos/common/app_init.c b/vision_apps/platform/j784s4/rtos/common/app_init.c
index a7b1ffad..ae063360 100755
--- a/vision_apps/platform/j784s4/rtos/common/app_init.c
+++ b/vision_apps/platform/j784s4/rtos/common/app_init.c
@@ -697,6 +697,8 @@ int32_t appInit()
     }
     #endif
 
+   
+#if 0
     #ifdef ENABLE_ETHFW
     status = appEthFwInit();
     APP_ASSERT_SUCCESS(status);
@@ -705,7 +707,7 @@ int32_t appInit()
 
     appLogWaitMsecs(50); /* Temporary workaround for ETHFW-1629 */
     #endif
-
+#endif
     #ifdef ENABLE_FVID2
     status = appFvid2Init();
     APP_ASSERT_SUCCESS(status);
diff --git a/vision_apps/platform/j784s4/rtos/mcu2_0/main.c b/vision_apps/platform/j784s4/rtos/mcu2_0/main.c
index b7e59c54..ccb7e4eb 100755
--- a/vision_apps/platform/j784s4/rtos/mcu2_0/main.c
+++ b/vision_apps/platform/j784s4/rtos/mcu2_0/main.c
@@ -307,11 +307,11 @@ static void appDSS(void* a0, void* a1)
 	appLogPrintf("appDSS: End!\n");
     return;
 }
-
+int enet_hello_main(void);
 void SPI_test_single_channel(void);
 static void appSPI(void* a0, void* a1)
 {
-    int32_t retVal = CSL_PASS;
+    int32_t retVal = CSL_PASS,status = 0;
 	
 	while(g_app_init_flag == 0)
 	{
@@ -320,7 +320,7 @@ static void appSPI(void* a0, void* a1)
 	appLogPrintf("***** appSPI Enter! flag:%d *****\n",g_app_init_flag);
 
 	#if 1
-	char delay_s = 20;
+	char delay_s = 35;
 	while(delay_s --)
 	{
 		Osal_delay(1000);
@@ -328,7 +328,14 @@ static void appSPI(void* a0, void* a1)
 	}
 	#endif
 	
-	SPI_test_single_channel();
+	#if 1
+    status = appEthFwInit();
+	enet_hello_main();
+    APP_ASSERT_SUCCESS(status);
+    status = appEthFwRemoteServerInit();
+    APP_ASSERT_SUCCESS(status);
+	#endif
+	//enet_hello_main();
 
 	appLogPrintf("appSPI: End!\n");
 }
diff --git a/vision_apps/utils/ethfw/src/app_ethfw_freertos.c b/vision_apps/utils/ethfw/src/app_ethfw_freertos.c
index 7a62e997..993d5c68 100644
--- a/vision_apps/utils/ethfw/src/app_ethfw_freertos.c
+++ b/vision_apps/utils/ethfw/src/app_ethfw_freertos.c
@@ -88,10 +88,10 @@ static uint8_t gEthAppLwipStackBuf[ETHAPP_LWIP_TASK_STACKSIZE] __attribute__ ((s
 #endif
 
 /* DHCP or static IP */
-#define ETHAPP_LWIP_USE_DHCP            (1)
+#define ETHAPP_LWIP_USE_DHCP            (0)
 #if !ETHAPP_LWIP_USE_DHCP
-#define ETHFW_SERVER_IPADDR(addr)       IP4_ADDR((addr), 192,168,1,200)
-#define ETHFW_SERVER_GW(addr)           IP4_ADDR((addr), 192,168,1,1)
+#define ETHFW_SERVER_IPADDR(addr)       IP4_ADDR((addr), 192,168,11,200)
+#define ETHFW_SERVER_GW(addr)           IP4_ADDR((addr), 192,168,11,1)
 #define ETHFW_SERVER_NETMASK(addr)      IP4_ADDR((addr), 255,255,255,0)
 #endif
 
@@ -147,7 +147,7 @@ static EthAppObj gEthAppObj =
     .hUdmaDrv = NULL,
     .instId   = 0U,
 };
-
+#if 1
 static Enet_MacPort gEthAppPorts[] =
 {
 #if defined(SOC_J721E)
@@ -171,6 +171,12 @@ static Enet_MacPort gEthAppPorts[] =
 #endif
 };
 
+#else
+static Enet_MacPort gEthAppPorts[] =
+{
+    ENET_MAC_PORT_1, /* SGMII main */
+};
+#endif
 #if defined(ETHFW_GPTP_SUPPORT)
 static Enet_MacPort gEthAppSwitchPorts[]=
 {
@@ -444,7 +450,7 @@ int32_t appEthFwInit()
     int32_t status = ETHAPP_OK;
     uint32_t flags = 0U;
 
-    appLogPrintf("ETHFW: Init ... !!!\n");
+    appLogPrintf("dans--ETHFW: Init ... !!!\n");
 
     gEthAppObj.coreId = EnetSoc_getCoreId();
 
@@ -456,6 +462,7 @@ int32_t appEthFwInit()
     if (status == ENET_SOK)
     {
         EthFwTrace_init(&gEthApp_traceCfg);
+        //appLogPrintf("dans--EthFwTrace_init\n");
     }
 
     /* Board related initialization */
@@ -466,6 +473,8 @@ int32_t appEthFwInit()
 #endif
 #elif defined(SOC_J784S4)
     flags |= (ETHFW_BOARD_QENET_ENABLE | ETHFW_BOARD_SERDES_CONFIG);
+    //flags |= (ETHFW_BOARD_ENET_BRIDGE_ENABLE | ETHFW_BOARD_SERDES_CONFIG);
+    
 #endif
 
     /* Board related initialization */
@@ -479,6 +488,7 @@ int32_t appEthFwInit()
     if (status == ENET_SOK)
     {
         gEthAppObj.hUdmaDrv = appUdmaGetObj();
+        //appLogPrintf("dans--appUdmaGetObj\n");
         if (gEthAppObj.hUdmaDrv == NULL)
         {
             appLogPrintf("ETHFW: ERROR: failed to open UDMA driver\n");
@@ -489,6 +499,7 @@ int32_t appEthFwInit()
 #if defined(ETHFW_GPTP_SUPPORT)
     /* Create semaphore used to synchronize MAC alloc by lwIP which is required and
      * shared with the gPTP stack */
+    //appLogPrintf("dans--000000000000\n");
     if (status == ETHAPP_OK)
     {
         SemaphoreP_Params_init(&semParams);
@@ -604,7 +615,7 @@ static int32_t EthApp_initEthFw(void)
     uint32_t poolSize;
     int32_t status = ETHAPP_OK;
     int32_t i;
-
+    //appLogPrintf("dans--EthApp_initEthFw\n");
     /* Set EthFw config params */
     EthFw_initConfigParams(gEthAppObj.enetType, &ethFwCfg);
 
@@ -746,7 +757,7 @@ static void EthApp_lwipMain(void *a0,
 {
     err_t err;
     sys_sem_t initSem;
-
+    //appLogPrintf("dans--EthApp_lwipMain\n");
     appUtilsTaskInit();
 
     /* initialize lwIP stack and network interfaces */
@@ -799,12 +810,12 @@ static void EthApp_initNetif(void)
     ip4_addr_set_zero(&netmask);
 
 #if ETHAPP_LWIP_USE_DHCP
-    appLogPrintf("Starting lwIP, local interface IP is dhcp-enabled\n");
+    appLogPrintf("Starting lwIP, dans --local interface IP is dhcp-enabled\n");
 #else /* ETHAPP_LWIP_USE_DHCP */
     ETHFW_SERVER_GW(&gw);
     ETHFW_SERVER_IPADDR(&ipaddr);
     ETHFW_SERVER_NETMASK(&netmask);
-    appLogPrintf("Starting lwIP, local interface IP is %s\n", ip4addr_ntoa(&ipaddr));
+    appLogPrintf("Starting lwIP, dans --local interface IP is %s\n", ip4addr_ntoa(&ipaddr));
 #endif /* ETHAPP_LWIP_USE_DHCP */
 
 #if defined(ETHAPP_ENABLE_INTERCORE_ETH)

The log is as follows:

oot@j784s4-evm:~# /opt/vision_apps/vision_apps_init.sh 
root@j784s4-evm:~# [MCU2_0]      4.652839 s: CIO: Init ... Done !!!
[MCU2_0]      4.652875 s: ### CPU Frequency = 1000000000 Hz
[MCU2_0]      4.652899 s: CPU is running FreeRTOS
[MCU2_0]      4.652916 s: APP: Init ... !!!
[MCU2_0]      4.652948 s: SCICLIENT: Init ... !!!
[MCU2_0]      4.653076 s: SCICLIENT: DMSC FW version [9.1.2--v09.01.02 (Kool Koala)]
[MCU2_0]      4.653104 s: SCICLIENT: DMSC FW revision 0x9  
[MCU2_0]      4.653124 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_0]      4.653144 s: SCICLIENT: Init ... Done !!!
[MCU2_0]      4.653162 s: UDMA: Init ... !!!
[MCU2_0]      4.654017 s: UDMA: Init ... Done !!!
[MCU2_0]      4.654049 s: UDMA: Init for CSITX/CSIRX ... !!!
[MCU2_0]      4.654483 s: UDMA: Init for CSITX/CSIRX ... Done !!!
[MCU2_0]      4.654512 s: MEM: Init ... !!!
[MCU2_0]      4.654536 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ bc800000 of size 268435456 bytes !!!
[MCU2_0]      4.654580 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 60000000 of size 262144 bytes !!!
[MCU2_0]      4.654615 s: MEM: Init ... Done !!!
[MCU2_0]      4.654630 s: IPC: Init ... !!!
[MCU2_0]      4.654666 s: IPC: 11 CPUs participating in IPC !!!
[MCU2_0]      4.654704 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_0]     15.071952 s: IPC: HLOS is ready !!!
[MCU2_0]     15.079463 s: IPC: Init ... Done !!!
[MCU2_0]     15.079502 s: APP: Syncing with 10 CPUs ... !!!
[MCU2_0]     16.020619 s: APP: Syncing with 10 CPUs ... Done !!!
[MCU2_0]     16.020651 s: REMOTE_SERVICE: Init ... !!!
[MCU2_0]     16.021475 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_0]     16.021512 s: FVID2: Init ... !!!
[MCU2_0]     16.021557 s: FVID2: Init ... Done !!!
[MCU2_0]     16.021650 s: DSS: Init ... !!!
[MCU2_0]     16.021670 s: DSS: Display type is eDP !!!
[MCU2_0]     16.021695 s: DSS: M2M Path is enabled !!!
[MCU2_0]     16.021715 s: DSS: SoC init ... !!!
[MCU2_0]     16.023350 s: DSS: SoC init ... Done !!!
[MCU2_0]     16.023373 s: DSS: Board init ... !!!
[MCU2_0]     16.023390 s: DSS: Board init ... Done !!!
[MCU2_0]     16.042371 s: DSS: Init ... Done !!!
[MCU2_0]     16.042417 s: VHWA: VPAC Init ... !!!
[MCU2_0]     16.042537 s: VHWA: LDC Init ... !!!
[MCU2_0]     16.044191 s: VHWA: LDC Init ... Done !!!
[MCU2_0]     16.044226 s: VHWA: MSC Init ... !!!
[MCU2_0]     16.050648 s: VHWA: MSC Init ... Done !!!
[MCU2_0]     16.050681 s: VHWA: NF Init ... !!!
[MCU2_0]     16.051591 s: VHWA: NF Init ... Done !!!
[MCU2_0]     16.051624 s: VHWA: VISS Init ... !!!
[MCU2_0]     16.057000 s: VHWA: VISS Init ... Done !!!
[MCU2_0]     16.057041 s: VHWA: VPAC Init ... Done !!!
[MCU2_0]     16.057075 s:  VX_ZONE_INIT:Enabled
[MCU2_0]     16.057092 s:  VX_ZONE_ERROR:Enabled
[MCU2_0]     16.057109 s:  VX_ZONE_WARNING:Enabled
[MCU2_0]     16.060072 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU2_0]     16.060104 s: APP: OpenVX Target kernel init ... !!!
[MCU2_0]     16.067237 s: APP: Register tivxRegisterFrontCameraTargetIpuKernels to CPU_mcu2_0 !!!
[MCU2_0]     16.067338 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_0]     16.067363 s: CSI2RX: Init ... !!!
[MCU2_0]     16.067842 s: CSI2RX: Init ... Done !!!
[MCU2_0]     16.067867 s: CSI2TX: Init ... !!!
[MCU2_0]     16.068104 s: CSI2TX: Init ... Done !!!
[MCU2_0]     16.068123 s: ISS: Init ... !!!
[MCU2_0]     16.068148 s: IssSensor_Init ... Done !!!
[MCU2_0]     16.068207 s: IttRemoteServer_Init ... Done !!!
[MCU2_0]     16.068225 s: ISS: Init ... Done !!!
[MCU2_0]     16.068244 s: VISS REMOTE SERVICE: Init ... !!!
[MCU2_0]     16.068290 s: VISS REMOTE SERVICE: Init ... Done !!!
[MCU2_0]     16.068311 s: UDMA Copy: Init ... !!!
[MCU2_0]     16.069221 s: UDMA Copy: Init ... Done !!!
[MCU2_0]     16.069287 s: APP: Init ... Done !!!
[MCU2_0]     16.069311 s: APP: Run ... !!!
[MCU2_0]     16.069329 s: IPC: Starting echo test ...
[MCU2_0]     16.070497 s: APP: Run ... Done !!!
[MCU2_0]     16.077982 s: ****** appMain: Init completed! *****
[MCU2_0]     16.079167 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[.] mcu3_1[.] mcu4_0[.] mcu4_1[.] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.] 
[MCU2_0]     16.079278 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[.] mcu4_0[.] mcu4_1[.] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.] 
[MCU2_0]     16.079352 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[.] mcu4_1[.] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.] 
[MCU2_0]     16.079422 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[.] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.] 
[MCU2_0]     16.079490 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.] 
[MCU2_0]     16.079556 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[.] c7x_3[.] c7x_4[.] 
[MCU2_0]     16.079626 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[.] c7x_4[.] 
[MCU2_0]     16.079698 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[.] 
[MCU2_0]     16.079766 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P] 
[MCU2_0]     16.152687 s: ***** appSPI Enter! flag:1 *****
[MCU2_0]     17.152682 s: appSPI Delay......(34)
[MCU2_0]     18.152681 s: appSPI Delay......(33)
[MCU2_0]     19.152681 s: appSPI Delay......(32)
[MCU2_0]     20.152681 s: appSPI Delay......(31)
[MCU2_0]     21.152681 s: appSPI Delay......(30)
[MCU2_0]     22.152681 s: appSPI Delay......(29)
[MCU2_0]     23.152681 s: appSPI Delay......(28)
[MCU2_0]     24.152681 s: appSPI Delay......(27)
[MCU2_0]     25.152681 s: appSPI Delay......(26)
[MCU2_0]     26.152681 s: appSPI Delay......(25)
[MCU2_0]     27.152681 s: appSPI Delay......(24)
[MCU2_0]     28.152681 s: appSPI Delay......(23)
[MCU2_0]     29.152681 s: appSPI Delay......(22)
[MCU2_0]     30.152681 s: appSPI Delay......(21)
[MCU2_0]     31.152681 s: appSPI Delay......(20)
[MCU2_0]     32.152681 s: appSPI Delay......(19)
[MCU2_0]     33.152681 s: appSPI Delay......(18)
[MCU2_0]     34.152681 s: appSPI Delay......(17)
[MCU2_0]     35.152681 s: appSPI Delay......(16)
[MCU2_0]     36.152681 s: appSPI Delay......(15)
[MCU2_0]     37.152681 s: appSPI Delay......(14)
[MCU2_0]     38.152681 s: appSPI Delay......(13)
[MCU2_0]     39.152681 s: appSPI Delay......(12)
[MCU2_0]     40.152681 s: appSPI Delay......(11)
[MCU2_0]     41.152681 s: appSPI Delay......(10)
[MCU2_0]     42.152681 s: appSPI Delay......(9)
[MCU2_0]     43.152681 s: appSPI Delay......(8)
[MCU2_0]     44.152681 s: appSPI Delay......(7)
[MCU2_0]     45.152681 s: appSPI Delay......(6)
[MCU2_0]     46.152681 s: appSPI Delay......(5)
[MCU2_0]     47.152681 s: appSPI Delay......(4)
[MCU2_0]     48.152681 s: appSPI Delay......(3)
[MCU2_0]     49.152681 s: appSPI Delay......(2)
[MCU2_0]     50.152681 s: appSPI Delay......(1)
[MCU2_0]     51.152681 s: appSPI Delay......(0)
[MCU2_0]     51.152699 s: dans--ETHFW: Init ... !!!
[MCU2_0]     51.258633 s: ETHFW: dans--Warning: Using 6 random MAC address(es)
[MCU2_0]     51.258672 s: ETHFW: Warning: Using 6 MAC address(es) from static pool
[MCU2_0]     51.258804 s: ETHFW: dans--CPSW recovery is not enabled
[MCU2_0]     51.258859 s: ETHFW: dans--Shared multicasts:
[MCU2_0]     51.258907 s: ETHFW:  dans-- 01:00:5e:00:00:01
[MCU2_0]     51.258932 s: ETHFW:  dans-- 01:00:5e:00:00:fb
[MCU2_0]     51.258957 s: ETHFW:  dans-- 01:00:5e:00:00:fc
[MCU2_0]     51.258981 s: ETHFW:  dans-- 33:33:00:00:00:01
[MCU2_0]     51.259018 s: ETHFW:  dans-- 33:33:ff:1d:92:c2
[MCU2_0]     51.259043 s: ETHFW:  dans-- 01:80:c2:00:00:00
[MCU2_0]     51.259067 s: ETHFW:  dans-- 01:80:c2:00:00:03
[MCU2_0]     51.259088 s: ETHFW: dans--Reserved multicasts:
[MCU2_0]     51.259115 s: ETHFW: dans--  01:80:c2:00:00:0e
[MCU2_0]     51.259140 s: ETHFW: dans--  01:1b:19:00:00:00
[MCU2_0]     51.259274 s: dans---MCM_GET_HANDLE
[MCU2_0]     51.259300 s: dans--EnetMcm: CPSW_9G on MAIN NAVSS
[MCU2_0]     51.269940 s: dans111---PHY 0 is alive
[MCU2_0]     51.269973 s: dans111---PHY 1 is alive
[MCU2_0]     51.269995 s: dans111---PHY 2 is no  alive
[MCU2_0]     51.270016 s: dans111---PHY 3 is no  alive
[MCU2_0]     51.270036 s: dans111---PHY 4 is no  alive
[MCU2_0]     51.270057 s: dans111---PHY 5 is no  alive
[MCU2_0]     51.270077 s: dans111---PHY 6 is no  alive
[MCU2_0]     51.270097 s: dans111---PHY 7 is no  alive
[MCU2_0]     51.270118 s: dans111---PHY 8 is no  alive
[MCU2_0]     51.270138 s: dans111---PHY 9 is no  alive
[MCU2_0]     51.270159 s: dans111---PHY 10 is no  alive
[MCU2_0]     51.270180 s: dans111---PHY 11 is no  alive
[MCU2_0]     51.270202 s: dans111---PHY 12 is no  alive
[MCU2_0]     51.270223 s: dans111---PHY 13 is no  alive
[MCU2_0]     51.270243 s: dans111---PHY 14 is no  alive
[MCU2_0]     51.270264 s: dans111---PHY 15 is no  alive
[MCU2_0]     51.270285 s: dans111---PHY 16 is no  alive
[MCU2_0]     51.270305 s: dans111---PHY 17 is no  alive
[MCU2_0]     51.270326 s: dans111---PHY 18 is no  alive
[MCU2_0]     51.270346 s: dans111---PHY 19 is no  alive
[MCU2_0]     51.270367 s: dans111---PHY 20 is no  alive
[MCU2_0]     51.270387 s: dans111---PHY 21 is no  alive
[MCU2_0]     51.270407 s: dans111---PHY 22 is no  alive
[MCU2_0]     51.270428 s: dans111---PHY 23 is no  alive
[MCU2_0]     51.270448 s: dans111---PHY 24 is no  alive
[MCU2_0]     51.270469 s: dans111---PHY 25 is no  alive
[MCU2_0]     51.270490 s: dans111---PHY 26 is no  alive
[MCU2_0]     51.270510 s: dans111---PHY 27 is no  alive
[MCU2_0]     51.270531 s: dans111---PHY 28 is no  alive
[MCU2_0]     51.270551 s: dans111---PHY 29 is no  alive
[MCU2_0]     51.270572 s: dans111---PHY 30 is no  alive
[MCU2_0]     51.270604 s: EnetPhy_initCfg: dans=EnetPhy_initCfg =0
[MCU2_0]     51.270628 s: 
[MCU2_0]     51.270815 s: CpswMacPort_configSgmii: dans123=ENET_MAC_SGMIIMODE_SGMII_AUTONEG_MASTER =0
[MCU2_0]     51.270856 s: 
[MCU2_0]     51.271000 s: EnetPhy_open: dans=EnetPhy_open =1
[MCU2_0]     51.271023 s: 
[MCU2_0]     51.271046 s: EnetPhy_open: dans=EnetPhy_open111
[MCU2_0]     51.271066 s: 
[MCU2_0]     51.271208 s: EnetPhy_getId: dans=EnetPhy_getId0000 =732 =33
[MCU2_0]     51.271232 s: 
[MCU2_0]     51.271256 s: RTL9010_isPhyDevSupported: dans--PHY 1: RTL9010_isPhyDevSupported
[MCU2_0]     51.271283 s: 
[MCU2_0]     51.271537 s: RTL9010Bx_Read_SoftConfig: dans=RTL9010Bx_Read_SoftConfig reg0==140=reg1==d=reg2==1c=reg3==cb30
[MCU2_0]     51.271570 s: 
[MCU2_0]     51.271833 s: RTL9010Bx_Read_SoftConfig: dans=RTL9010Bx_Read_SoftConfig reg09==800=regA==7000=regD==0=regE==0
[MCU2_0]     51.271867 s: 
[MCU2_0]     51.272005 s: RTL9010Bx_Read_SoftConfig: dans=RTL9010Bx_Read_SoftConfig Page0xA60 reg0x10==3337
[MCU2_0]     51.272036 s: 
[MCU2_0]     51.272055 s: RTL9010Ax_Initial_Configuration: dans=RTL9010Ax_Initial_Configuration---0
[MCU2_0]     51.272083 s: 
[MCU2_0]     51.274333 s: RTL9010Ax_Initial_Configuration: dans=soft-reset000====8100
[MCU2_0]     51.274360 s: 
[MCU2_0]     51.274420 s: RTL9010Ax_Initial_Configuration: dans=soft-reset000====8100
[MCU2_0]     51.274446 s: 
[MCU2_0]     51.274508 s: RTL9010Ax_Initial_Configuration: dans=soft-reset000====140
[MCU2_0]     51.274533 s: 
[MCU2_0]     51.274553 s: RTL9010Bx_Initial_SGMI_Configuration: dans=RTL9010Bx_Initial_SGMI_Configuration---0
[MCU2_0]     51.274583 s: 
[MCU2_0]     51.287150 s: RTL9010Bx_Initial_SGMI_Configuration: dans=soft-reset1111====8100
[MCU2_0]     51.287183 s: 
[MCU2_0]     51.287234 s: RTL9010Bx_Initial_SGMI_Configuration: dans=soft-reset1111====8100
[MCU2_0]     51.287261 s: 
[MCU2_0]     51.287323 s: RTL9010Bx_Initial_SGMI_Configuration: dans=soft-reset1111====140
[MCU2_0]     51.287349 s: 
[MCU2_0]     51.287368 s: RTL9010Ax_Initial_Configuration_Check: dans=RTL9010Ax_Initial_Configuration_Check
[MCU2_0]     51.287398 s: 
[MCU2_0]     51.289596 s: RTL9010Ax_Initial_with_SGMII_Configuration_Check: dans=RTL9010Ax_Initial_with_SGMII_Configuration_Check
[MCU2_0]     51.289633 s: 
[MCU2_0]     51.311742 s: RTL9010_isPhyDevSupported: dans=RTL9010_isPhyDevSupported---end
[MCU2_0]     51.311771 s: 
[MCU2_0]     51.311798 s: EnetPhy_bindDriver: PHY 1: OUI:000732 Model:33 Ver:00 <-> 'RTL9010AS' : OK
[MCU2_0]     51.311826 s: 
[MCU2_0]     51.311850 s: EnetPhy_initCfg: dans=EnetPhy_initCfg =0
[MCU2_0]     51.311873 s: 
[MCU2_0]     51.312040 s: CpswMacPort_configSgmii: dans123=ENET_MAC_SGMIIMODE_SGMII_WITH_PHY =2
[MCU2_0]     51.312075 s: 
[MCU2_0]     51.312215 s: EnetPhy_open: dans=EnetPhy_open =17
[MCU2_0]     51.312238 s: 
[MCU2_0]     51.312264 s: EnetPhy_initCfg: dans=EnetPhy_initCfg =0
[MCU2_0]     51.312285 s: 
[MCU2_0]     51.312442 s: CpswMacPort_configSgmii: dans123=ENET_MAC_SGMIIMODE_SGMII_WITH_PHY =3
[MCU2_0]     51.312476 s: 
[MCU2_0]     51.312613 s: EnetPhy_open: dans=EnetPhy_open =18
[MCU2_0]     51.312634 s: 
[MCU2_0]     51.312654 s: EnetPhy_initCfg: dans=EnetPhy_initCfg =0
[MCU2_0]     51.312675 s: 
[MCU2_0]     51.312830 s: CpswMacPort_configSgmii: dans123=ENET_MAC_SGMIIMODE_SGMII_WITH_PHY =4
[MCU2_0]     51.312864 s: 
[MCU2_0]     51.313001 s: EnetPhy_open: dans=EnetPhy_open =19
[MCU2_0]     51.313023 s: 
[MCU2_0]     51.315923 s: ETHFW: 0 VLAN entries added in ALE table
[MCU2_0]     51.316106 s: 
[MCU2_0] ETHFW Version   : 0.04.00
[MCU2_0]     51.316133 s: ETHFW Build Date: Jul  2, 2024
[MCU2_0]     51.316151 s: ETHFW Build Time: 16:24:52
[MCU2_0]     51.316168 s: ETHFW Commit SHA: 0bf6a31c
[MCU2_0]     51.316214 s: ETHFW: Init ... DONE !!!
[MCU2_0]     51.316414 s: unibase-1.1.4-jacinto
[MCU2_0]     51.316916 s: Starting lwIP, dans --local interface IP is 192.168.11.200
[MCU2_0]     51.317466 s: RTOS: semhandle was NULL
[MCU2_0]     51.317534 s: dans---MCM_GET_HANDLE
[MCU2_0]     51.322684 s: ETHFW: Host MAC address: 70:77:80:b1:be:80
[MCU2_0]     51.323896 s: ETHFW: Enable gPTP on MAC port 3 (tilld3)
[MCU2_0]     51.323930 s: ETHFW: Enable gPTP on MAC port 5 (tilld5)
[MCU2_0]     51.324016 s: ETHFW: TimeSync PTP enabled
[MCU2_0]     51.324049 s: 
[MCU2_0]     51.324064 s: dans--Enet Hello World 0
[MCU2_0]     51.324517 s: [dans] Board_CfgSgmii_serdes1 start
[MCU2_0]     51.324549 s: Board_CfgSgmii_serdes1 82 
[MCU2_0]     51.324573 s: Board_CfgSgmii_serdes1 110 
[MCU2_0]     51.324611 s: Board_CfgSgmii_serdes1 113 
[MCU2_0]     51.324637 s: Board_CfgSgmii_serdes1 140 
[MCU2_0]     51.324686 s: Board_CfgSgmii_serdes1 148 
[MCU2_0]     51.324712 s: Board_CfgSgmii_serdes1 154 
[MCU2_0]     51.324737 s: Board_CfgSgmii_serdes1 158 
[MCU2_0]     51.324796 s: Board_CfgSgmii_serdes1 167 
[MCU2_0]     51.325055 s: Board_CfgSgmii_serdes1 175 
[MCU2_0]     51.325074 s: [dans] Board_CfgSgmii_serdes1 end
[MCU2_0]     51.325096 s: 
[MCU2_0]     51.325111 s: dans--Enet Hello World 1
[MCU2_0]     51.325131 s: 
[MCU2_0]     51.325146 s: dans--Enet Hello World 2
[MCU2_0]     51.325162 s: ETHFW: Remove server Init ... !!!
[MCU2_0]     51.325253 s: ETHFW: Virtual port configuration:
[MCU2_0]     51.325831 s: ETHFW: CpswProxyServer: initialization completed (core: mcu2_0)
[MCU2_0]     51.325867 s: ETHFW: Remove server Init ... DONE !!!
[MCU2_0]     51.325887 s: appSPI: End!
[MCU2_0]     51.326814 s: [LWIPIF_LWIP] Enet LLD netif initialized successfully
[MCU2_0]     51.326875 s: Added interface 'ti0', IP is 192.168.11.200
[MCU2_0]     51.327128 s: dans---MCM_GET_HANDLE
[MCU2_0]     51.327177 s: dans---MCM_GET_HANDLE
[MCU2_0]     51.337011 s: dans---MCM_GET_HANDLE
[MCU2_0]     51.337788 s: dans---MCM_GET_HANDLE
[MCU2_0]     51.337889 s: dans---MCM_GET_HANDLE
[MCU2_0]     51.356775 s: ETHFW: VIRT_PORT_INFO | C2S | core=0 endpt=1026
[MCU2_0]     51.356816 s: ETHFW: VIRT_PORT_INFO | S2C | switchPortMask=1 macPortMask=10
[MCU2_0]     51.356922 s: ETHFW: ATTACH_EXT | C2S | core=0 endpt=1026 virtPort=0
[MCU2_0]     51.356977 s: dans---MCM_GET_HANDLE
[MCU2_0]     51.357106 s: ETHFW: ATTACH_EXT | S2C | token=0 rxMtu=1522 features=8 flow=114,0 rxPsil=0x4a00 txPsil=0xca00 macAddr=70:ef:53:1a:15:2d
[MCU2_0]     51.357212 s: ETHFW: ATTACH_EXT | C2S | core=0 endpt=1026 virtPort=4
[MCU2_0]     51.357260 s: dans---MCM_GET_HANDLE
[MCU2_0]     51.357337 s: ETHFW: ATTACH_EXT | S2C | token=400 rxMtu=1522 features=0 flow=114,1 rxPsil=0x4a00 txPsil=0xca01 macAddr=70:a3:e9:ed:05:ec
[MCU2_0]     51.437474 s: ETHFW: REGISTER_MAC | C2S | core=0 endpt=1026 token=0 macAdd=70:ef:53:1a:15:2d flowIdx=114,0
[MCU2_0]     51.443139 s: Cpsw_ioctlInternal: Registered MAC address (ALE entry=8, policer entry=1)
[MCU2_0]     51.443181 s: 
[MCU2_0]     51.449813 s: ETHFW: REGISTER_MAC | S2C | status=0
[MCU2_0]     51.459668 s: ETHFW: ADD_FILTER_MAC | C2S | core=0 endpt=1026 token=0 macAdd=33:33:00:00:00:01 vlanId=65535 flowIdx=114,0
[MCU2_0]     51.462495 s: filterAddMacSharedCb: Address found: 33:33:0:0:0:1
[MCU2_0]     51.468098 s: ETHFW: ADD_FILTER_MAC | S2C | status=0
[MCU2_0]     51.468237 s: ETHFW: ADD_FILTER_MAC | C2S | core=0 endpt=1026 token=0 macAdd=01:00:5e:00:00:01 vlanId=65535 flowIdx=114,0
[MCU2_0]     51.471043 s: filterAddMacSharedCb: Address found: 1:0:5e:0:0:1
[MCU2_0]     51.476635 s: ETHFW: ADD_FILTER_MAC | S2C | status=0
[MCU2_0]     51.476771 s: ETHFW: ADD_FILTER_MAC | C2S | core=0 endpt=1026 token=0 macAdd=33:33:ff:1a:15:2d vlanId=65535 flowIdx=114,0
[MCU2_0]     51.482402 s: ETHFW: ADD_FILTER_MAC | S2C | status=0
[MCU2_0]     51.482504 s: ETHFW: ADD_FILTER_MAC | C2S | core=0 endpt=1026 token=0 macAdd=01:80:c2:00:00:00 vlanId=65535 flowIdx=114,0
[MCU2_0]     51.485314 s: filterAddMacSharedCb: Address found: 1:80:c2:0:0:0
[MCU2_0]     51.490909 s: ETHFW: ADD_FILTER_MAC | S2C | status=0
[MCU2_0]     51.491014 s: ETHFW: ADD_FILTER_MAC | C2S | core=0 endpt=1026 token=0 macAdd=01:80:c2:00:00:03 vlanId=65535 flowIdx=114,0
[MCU2_0]     51.493849 s: filterAddMacSharedCb: Address found: 1:80:c2:0:0:3
[MCU2_0]     51.499570 s: ETHFW: ADD_FILTER_MAC | S2C | status=0
[MCU2_0]     51.499746 s: ETHFW: ADD_FILTER_MAC | C2S | core=0 endpt=1026 token=0 macAdd=01:80:c2:00:00:0e vlanId=65535 flowIdx=114,0
[MCU2_0]     51.499795 s: ETHFW: ADD_FILTER_MAC | S2C | status=0
[MCU2_0]     51.500999 s: ETHFW: REGISTER_MAC | C2S | core=0 endpt=1026 token=400 macAdd=70:a3:e9:ed:05:ec flowIdx=114,1
[MCU2_0]     51.503885 s: ETHFW: REGISTER_MAC | S2C | status=0
[MCU2_0]     51.512723 s: EnetPhy_tick: dans=EnetPhy_resetWaitState =1
[MCU2_0]     51.512755 s: 
[MCU2_0]     53.358365 s: ETHFW: ADD_FILTER_MAC | C2S | core=0 endpt=1026 token=0 macAdd=33:33:00:00:00:fb vlanId=65535 flowIdx=114,0
[MCU2_0]     53.364127 s: ETHFW: ADD_FILTER_MAC | S2C | status=0

Q1: Can the above logs indicate that the configuration is correct?

Q2: How can I ping my PC through MAC_PORT1 now?

Best Regards

Hi,

Doredla Sudheer Kumar said:

Also, Link Up message for Port-1 also not observed. Can you please confirm is Link is Up or not?

For the above log, I did not see any error. How can I tell if macport1 link up?

sorry . Just accidentally some problem has been solved key.

Hi,

jin zhu said:

Also, Link Up message for Port-1 also not observed. Can you please confirm is Link is Up or not?

For the above log, I did not see any error. How can I tell if macport1 link up?

You will observe the Link Up message from EthFw for the Ports enabled.

Best Regards,
Sudheer

Doredla Sudheer Kumar said:

You will observe the Link Up message from EthFw for the Ports enabled.

I haven't seen it yet, but I see the following log:

[MCU2_0] 51.311798 s: EnetPhy_bindDriver: PHY 1: OUI:000732 Model:33 Ver:00 <-> 'RTL9010AS' : OK

The above log indicates that I have identified the phy device.

Hi,

jin zhu said:

[MCU2_0] 51.311798 s: EnetPhy_bindDriver: PHY 1: OUI:000732 Model:33 Ver:00 <-> 'RTL9010AS' : OK

The above log indicates that I have identified the phy device.

Yes. It doesn't  mean that  PHY Link is Up.

Best Regards,
Sudheer

Doredla Sudheer Kumar said:

Yes. It doesn't  mean that  PHY Link is Up.

After some modifications, the following error occurred. How can I solve it?

[ 45.157033] ti_cpsw_proxy_client virtio2.ti.ethfw.ethdevice.-1.114: failed to receive response. Response Timedout
[ 45.167290] ti_cpsw_proxy_client virtio2.ti.ethfw.ethdevice.-1.114: failed to add multicast mac filter err: -110
[ 45.701030] ti_cpsw_proxy_client virtio2.ti.ethfw.ethdevice.-1.114: failed to receive response. Response Timedout
[ 45.711274] ti_cpsw_proxy_client virtio2.ti.ethfw.ethdevice.-1.114: failed to add multicast mac filter err: -110

[MCU2_0]     31.628633 s: appSPI Delay......(20)
[MCU2_0]     32.628633 s: appSPI Delay......(19)
[MCU2_0]     33.628633 s: appSPI Delay......(18)
[MCU2_0]     34.628633 s: appSPI Delay......(17)
[MCU2_0]     35.628633 s: appSPI Delay......(16)
[MCU2_0]     36.628633 s: appSPI Delay......(15)
[MCU2_0]     37.628633 s: appSPI Delay......(14)
[MCU2_0]     38.628633 s: appSPI Delay......(13)
[MCU2_0]     39.628633 s: appSPI Delay......(12)
[MCU2_0]     40.628633 s: appSPI Delay......(11)
[MCU2_1]     41.562948 s: ============MCAN_Rd_init 1
[MCU2_1]     41.563155 s: MCAN_Rd_init() done!
[MCU2_1]     41.563189 s:  dans---appMain---counter= 25
[MCU2_0]     41.628633 s: appSPI Delay......(10)
[MCU2_0]     42.628633 s: appSPI Delay......(9)
[MCU2_0]     43.628633 s: appSPI Delay......(8)
[MCU2_0]     44.628633 s: appSPI Delay......(7)
[MCU2_0]     45.628633 s: appSPI Delay......(6)
[MCU2_0]     46.628633 s: appSPI Delay......(5)
[MCU2_0]     47.628633 s: appSPI Delay......(4)
[MCU2_0]     48.628633 s: appSPI Delay......(3)
[MCU2_0]     49.628633 s: appSPI Delay......(2)
[MCU2_0]     50.628633 s: appSPI Delay......(1)
[MCU2_0]     51.628633 s: appSPI Delay......(0)
[MCU2_0]     51.628651 s: dans--ETHFW: Init ... !!!
[MCU2_0]     51.734626 s: ETHFW: dans--Warning: Using 6 random MAC address(es)
[MCU2_0]     51.734664 s: ETHFW: Warning: Using 6 MAC address(es) from static pool
[MCU2_0]     51.734787 s: ETHFW: dans--CPSW recovery is not enabled
[MCU2_0]     51.734837 s: ETHFW: dans--Shared multicasts:
[MCU2_0]     51.734872 s: ETHFW:  dans-- 01:00:5e:00:00:01
[MCU2_0]     51.734897 s: ETHFW:  dans-- 01:00:5e:00:00:fb
[MCU2_0]     51.734922 s: ETHFW:  dans-- 01:00:5e:00:00:fc
[MCU2_0]     51.734947 s: ETHFW:  dans-- 33:33:00:00:00:01
[MCU2_0]     51.734972 s: ETHFW:  dans-- 33:33:ff:1d:92:c2
[MCU2_0]     51.734996 s: ETHFW:  dans-- 01:80:c2:00:00:00
[MCU2_0]     51.735020 s: ETHFW:  dans-- 0[   42.745487] virtio_rpmsg_bus virtio2: creating channel ti.ethfw.notifyservice addr 0x73
1:80:c2:00:00:03
[MCU2_0]     51.735042 s: ETHFW: dans--Reserv[   42.754477] virtio_rpmsg_bus virtio2: creating channel ti.ethfw.ethdevice addr 0x72
ed multicasts:
[MCU2_0]     51.735068 s: ETHFW: dans--  01:80:c2:00:00:0e
[MCU2_0]     51.735093 s: ETHFW: dans--  01:1b:19:00:00:00
[MCU2_0]     51.735233 s: dans---MCM_GET_HANDLE
[MC[   42.782049] ti_cpsw_proxy_client virtio2.ti.ethfw.ethdevice.-1.114: 1 Virtual Switch Port(s), 1 Virtual MAC Only Port(s)
U2_0]     51.735261 s: dans--EnetMcm: CPSW_9G on MAIN NAVSS
[M[   42.795094] ti_cpsw_proxy_client virtio2.ti.ethfw.ethdevice.-1.114: Virt Port: 0, Type: Switch Port, Iface: eth2, Token: 0
CU2_0]     51.746268 s: dans111---PHY 0 is alive
[MCU2_0]     [   42.811612] ti_cpsw_proxy_client virtio2.ti.ethfw.ethdevice.-1.114: Virt Port: 4, Type: MAC Port, Iface: eth3, Token: 400
51.746308 s: dans111---PHY 1 is alive
[MCU2_0]     51.746331 s: dans111---PHY 2 is no  alive
[MCU2_0]     51.746352 s: dans111---PHY 3 is no  alive
[MCU2_0]     51.746372 s: dans111---PHY 4 is no  alive
[MCU2_0]     51.746393 s: dans111---PHY 5 is no  alive
[MCU2_0]     51.746413 s: dans111---PHY 6 is no  alive
[MCU2_0]     51.746433 s: dans111---PHY 7 is no  alive
[MCU2_0]     51.746453 s: dans111---PHY 8 is no  alive
[MCU2_0]     51.746474 s: dans111---PHY 9 is no  alive
[MCU2_0]     51.746496 s: dans111---PHY 10 is no  alive
[MCU2_0]     51.746517 s: dans111---PHY 11 is no  alive
[MCU2_0]     51.746537 s: dans111---PHY 12 is no  alive
[MCU2_0]     51.746558 s: dans111---PHY 13 is no  alive
[MCU2_0]     51.746578 s: dans111---PHY [   42.893970] ti_cpsw_proxy_client virtio2.ti.ethfw.ethdevice.-1.114: started virt port: 0 on interface eth2
14 is no  alive
[MCU2_0]     51.746599 s: dans111---PHY 15 is no  alive
[MCU2_0]     51.746619 s: dans111---PHY 16 is no  alive
[MCU2_0]     51.746645 s: dans111---PHY 17 is no  alive
[   42.915901] ti_cpsw_proxy_client virtio2.ti.ethfw.ethdevice.-1.114: started virt port: 4 on interface eth3
[MCU2_0]     51.746666 s: dans111---PHY 18 is no  alive
[MCU2_0]     51.746686 s: dans111---PHY 19 is no  alive
[MCU2_0]     51.746707 s: dans111---PHY 20 is no  alive
[MCU2_0]     51.746727 s: dans111---PHY 21 is no  alive
[MCU2_0]     51.746748 s: dans111---PHY 22 is no  alive
[MCU2_0]     51.746768 s: dans111---PHY 23 is no  alive
[MCU2_0]     51.746788 s: dans111---PHY 24 is no  alive
[MCU2_0]     51.746809 s: dans111---PHY 25 is no  alive
[MCU2_0]     51.746829 s: dans111---PHY 26 is no  alive
[MCU2_0]     51.746850 s: dans111---PHY 27 is no  alive
[MCU2_0]     51.746871 s: dans111---PHY 28 is no  alive
[MCU2_0]     51.746892 s: dans111---PHY 29 is no  alive
[MCU2_0]     51.746912 s: dans111---PHY 30 is no  alive
[MCU2_0]     51.746942 s: EnetPhy_initCfg: dans=EnetPhy_initCfg =0
[MCU2_0]     51.746965 s: 
[MCU2_0]     51.747147 s: CpswMacPort_configSgmii: dans123=ENET_MAC_SGMIIMODE_SGMII_AUTONEG_MASTER =0
[MCU2_0]     51.747184 s: 
[MCU2_0]     51.747332 s: EnetPhy_open: dans=EnetPhy_open =1
[MCU2_0]     51.747355 s: 
[MCU2_0]     51.747376 s: EnetPhy_open: dans=EnetPhy_open hPhy->macCaps=94
[MCU2_0]     51.747399 s: 
[MCU2_0]     51.747420 s: EnetPhy_open: dans=EnetPhy_open111
[MCU2_0]     51.747440 s: 
[MCU2_0]     51.747585 s: EnetPhy_getId: dans=EnetPhy_getId0000 =732 =33
[MCU2_0]     51.747611 s: 
[MCU2_0]     51.747641 s: RTL9010_isPhyDevSupported: dans--PHY 1: RTL9010_isPhyDevSupported
[MCU2_0]     51.747668 s: 
[MCU2_0]     51.747912 s: RTL9010Bx_Read_SoftConfig: dans=RTL9010Bx_Read_SoftConfig reg0==140=reg1==d=reg2==1c=reg3==cb30
[MCU2_0]     51.747946 s: 
[MCU2_0]     51.748206 s: RTL9010Bx_Read_SoftConfig: dans=RTL9010Bx_Read_SoftConfig reg09==800=regA==7000=regD==0=regE==0
[MCU2_0]     51.748239 s: 
[MCU2_0]     51.748381 s: RTL9010Bx_Read_SoftConfig: dans=RTL9010Bx_Read_SoftConfig Page0xA60 reg0x10==3337
[MCU2_0]     51.748411 s: 
[MCU2_0]     51.748431 s: RTL9010Ax_Initial_Configuration: dans=RTL9010Ax_Initial_Configuration---0
[MCU2_0]     51.748458 s: 
[MCU2_0]     51.750707 s: RTL9010Ax_Initial_Configuration: dans=soft-reset000====8100
[MCU2_0]     51.750733 s: 
[MCU2_0]     51.750795 s: RTL9010Ax_Initial_Configuration: dans=soft-reset000====8100
[MCU2_0]     51.750820 s: 
[MCU2_0]     51.750883 s: RTL9010Ax_Initial_Configuration: dans=soft-reset000====140
[MCU2_0]     51.750907 s: 
[MCU2_0]     51.750927 s: RTL9010Bx_Initial_SGMI_Configuration: dans=RTL9010Bx_Initial_SGMI_Configuration---0
[MCU2_0]     51.750958 s: 
[MCU2_0]     51.763529 s: RTL9010Bx_Initial_SGMI_Configuration: dans=soft-reset1111====8100
[MCU2_0]     51.763561 s: 
[MCU2_0]     51.763642 s: RTL9010Bx_Initial_SGMI_Configuration: dans=soft-reset1111====8140
[MCU2_0]     51.763668 s: 
[MCU2_0]     51.763728 s: RTL9010Bx_Initial_SGMI_Configuration: dans=soft-reset1111====140
[MCU2_0]     51.763754 s: 
[MCU2_0]     51.763774 s: RTL9010Ax_Initial_Configuration_Check: dans=RTL9010Ax_Initial_Configuration_Check
[MCU2_0]     51.763804 s: 
[MCU2_0]     51.765942 s: RTL9010Ax_Initial_with_SGMII_Configuration_Check: dans=RTL9010Ax_Initial_with_SGMII_Configuration_Check
[MCU2_0]     51.765976 s: 
[MCU2_0]     51.788059 s: RTL9010_isPhyDevSupported: dans=RTL9010_isPhyDevSupported---end
[MCU2_0]     51.788087 s: 
[MCU2_0]     51.788114 s: EnetPhy_bindDriver: PHY 1: OUI:000732 Model:33 Ver:00 <-> 'RTL9010AS' : OK
[MCU2_0]     51.788142 s: 
[MCU2_0]     51.788166 s: EnetPhy_initCfg: dans=EnetPhy_initCfg =0
[MCU2_0]     51.788187 s: 
[MCU2_0]     51.788354 s: CpswMacPort_configSgmii: dans123=ENET_MAC_SGMIIMODE_SGMII_WITH_PHY =2
[MCU2_0]     51.788387 s: 
[MCU2_0]     51.788529 s: EnetPhy_open: dans=EnetPhy_open =17
[MCU2_0]     51.788550 s: 
[MCU2_0]     51.788569 s: EnetPhy_open: dans=EnetPhy_open hPhy->macCaps=94
[MCU2_0]     51.788592 s: 
[MCU2_0]     51.788615 s: EnetPhy_initCfg: dans=EnetPhy_initCfg =0
[MCU2_0]     51.788641 s: 
[MCU2_0]     51.788794 s: CpswMacPort_configSgmii: dans123=ENET_MAC_SGMIIMODE_SGMII_WITH_PHY =3
[MCU2_0]     51.788839 s: 
[MCU2_0]     51.788993 s: EnetPhy_open: dans=EnetPhy_open =18
[MCU2_0]     51.789014 s: 
[MCU2_0]     51.789032 s: EnetPhy_open: dans=EnetPhy_open hPhy->macCaps=94
[MCU2_0]     51.789055 s: 
[MCU2_0]     51.789075 s: EnetPhy_initCfg: dans=EnetPhy_initCfg =0
[MCU2_0]     51.789096 s: 
[MCU2_0]     51.789249 s: CpswMacPort_configSgmii: dans123=ENET_MAC_SGMIIMODE_SGMII_WITH_PHY =4
[MCU2_0]     51.789280 s: 
[MCU2_0]     51.789417 s: EnetPhy_open: dans=EnetPhy_open =19
[MCU2_0]     51.789438 s: 
[MCU2_0]     51.789456 s: EnetPhy_open: dans=EnetPhy_open hPhy->macCaps=94
[MCU2_0]     51.789479 s: 
[MCU2_0]     51.792382 s: ETHFW: 0 VLAN entries added in ALE table
[MCU2_0]     51.792572 s: 
[MCU2_0] ETHFW Version   : 0.04.00
[MCU2_0]     51.792601 s: ETHFW Build Date: Jul  3, 2024
[MCU2_0]     51.792620 s: ETHFW Build Time: 11:40:42
[MCU2_0]     51.792640 s: ETHFW Commit SHA: 0bf6a31c
[MCU2_0]     51.792676 s: ETHFW: Init ... DONE !!!
[MCU2_0]     51.792864 s: unibase-1.1.4-jacinto
[MCU2_0]     51.793358 s: Starting lwIP, dans --local interface IP is 192.168.11.200
[MCU2_0]     51.793943 s: dans---MCM_GET_HANDLE
[MCU2_0]     51.799074 s: ETHFW: Host MAC address: 70:05:54:6b:73:77
[MCU2_0]     51.800298 s: ETHFW: Enable gPTP on MAC port 3 (tilld3)
[MCU2_0]     51.800333 s: ETHFW: Enable gPTP on MAC port 5 (tilld5)
[MCU2_0]     51.800415 s: ETHFW: TimeSync PTP enabled
[MCU2_0]     51.800449 s: 
[MCU2_0]     51.800467 s: dans--Enet Hello World 0
[MCU2_0]     51.800922 s: [dans] Board_CfgSgmii_serdes1 start
[MCU2_0]     51.800955 s: Board_CfgSgmii_serdes1 82 
[MCU2_0]     51.800981 s: Board_CfgSgmii_serdes1 110 
[MCU2_0]     51.801020 s: Board_CfgSgmii_serdes1 113 
[MCU2_0]     51.801047 s: Board_CfgSgmii_serdes1 140 
[MCU2_0]     51.801089 s: Board_CfgSgmii_serdes1 148 
[MCU2_0]     51.801115 s: Board_CfgSgmii_serdes1 154 
[MCU2_0]     51.801140 s: Board_CfgSgmii_serdes1 158 
[MCU2_0]     51.801201 s: Board_CfgSgmii_serdes1 167 
[MCU2_0]     51.801497 s: Board_CfgSgmii_serdes1 175 
[MCU2_0]     51.801518 s: [dans] Board_CfgSgmii_serdes1 end
[MCU2_0]     51.801540 s: 
[MCU2_0]     51.801554 s: dans--Enet Hello World 1
[MCU2_0]     51.801574 s: 
[MCU2_0]     51.801588 s: dans--Enet Hello World 2
[MCU2_0]     51.801605 s: ETHFW: Remove server Init ... !!!
[MCU2_0]     51.801699 s: ETHFW: Virtual port configuration:
[MCU2_0]     51.802214 s: ETHFW: CpswProxyServer: initialization completed (core: mcu2_0)
[MCU2_0]     51.802249 s: ETHFW: Remove server Init ... DONE !!!
[MCU2_0]     51.802269 s: appSPI: End!
[MCU2_0]     51.803154 s: [LWIPIF_LWIP] Enet LLD netif initialized successfully
[MCU2_0]     51.803212 s: Added interface 'ti0', IP is 192.168.11.200
[MCU2_0]     51.803451 s: dans---MCM_GET_HANDLE
[MCU2_0]     51.803503 s: dans---MCM_GET_HANDLE
[MCU2_0]     51.813341 s: dans---MCM_GET_HANDLE
[MCU2_0]     51.814123 s: dans---MCM_GET_HANDLE
[MCU2_0]     51.814214 s: dans---MCM_GET_HANDLE
[MCU2_0]     51.833456 s: ETHFW: VIRT_PORT_INFO | C2S | core=0 endpt=1026
[MCU2_0]     51.833494 s: ETHFW: VIRT_PORT_INFO | S2C | switchPortMask=1 macPortMask=10
[MCU2_0]     51.833591 s: ETHFW: ATTACH_EXT | C2S | core=0 endpt=1026 virtPort=0
[MCU2_0]     51.833688 s: dans---MCM_GET_HANDLE
[MCU2_0]     51.833826 s: ETHFW: ATTACH_EXT | S2C | token=0 rxMtu=1522 features=8 flow=114,0 rxPsil=0x4a00 txPsil=0xca00 macAddr=70:9a:90:24:6c:90
[MCU2_0]     51.833938 s: ETHFW: ATTACH_EXT | C2S | core=0 endpt=1026 virtPort=4
[MCU2_0]     51.833984 s: dans---MCM_GET_HANDLE
[MCU2_0]     51.834065 s: ETHFW: ATTACH_EXT | S2C | token=400 rxMtu=1522 features=0 flow=114,1 rxPsil=0x4a00 txPsil=0xca01 macAddr=70:62:53:c4:8b:60
[MCU2_0]     51.888683 s: Cpsw_periodicTick: dans=Cpsw_periodicTick =8
[MCU2_0]     51.888716 s: 
[MCU2_0]     51.888736 s: EnetPhy_tick: dans=EnetPhy_foundState =1
[MCU2_0]     51.888759 s: 
[MCU2_0]     51.888905 s: Cpsw_periodicTick: dans=Cpsw_periodicTick =8
[MCU2_0]     51.888928 s: 
[MCU2_0]     51.888958 s: EnetPhy_tick: dans=EnetPhy_initState =17
[MCU2_0]     51.888980 s: 
[MCU2_0]     51.888998 s: Cpsw_periodicTick: dans=Cpsw_periodicTick =8
[MCU2_0]     51.889020 s: 
[MCU2_0]     51.889036 s: EnetPhy_tick: dans=EnetPhy_initState =18
[MCU2_0]     51.889057 s: 
[MCU2_0]     51.889074 s: Cpsw_periodicTick: dans=Cpsw_periodicTick =8
[MCU2_0]     51.889095 s: 
[MCU2_0]     51.889112 s: EnetPhy_tick: dans=EnetPhy_initState =19
[MCU2_0]     51.889133 s: 
[MCU2_0]     51.938252 s: ETHFW: REGISTER_MAC | C2S | core=0 endpt=1026 token=0 macAdd=70:9a:90:24:6c:90 flowIdx=114,0
[MCU2_0]     51.943902 s: Cpsw_ioctlInternal: Registered MAC address (ALE entry=8, policer entry=1)
[MCU2_0]     51.943940 s: 
[MCU2_0]     51.950541 s: ETHFW: REGISTER_MAC | S2C | status=0
[MCU2_0]     51.961099 s: ETHFW: ADD_FILTER_MAC | C2S | core=0 endpt=1026 token=0 macAdd=33:33:00:00:00:01 vlanId=65535 flowIdx=114,0
[MCU2_0]     51.963921 s: filterAddMacSharedCb: Address found: 33:33:0:0:0:1
[MCU2_0]     51.969482 s: ETHFW: ADD_FILTER_MAC | S2C | status=0
[MCU2_0]     51.969607 s: ETHFW: REGISTER_MAC | C2S | core=0 endpt=1026 token=400 macAdd=70:62:53:c4:8b:60 flowIdx=114,1
[MCU2_0]     51.972494 s: ETHFW: REGISTER_MAC | S2C | status=0
[MCU2_0]     51.972608 s: ETHFW: ADD_FILTER_MAC | C2S | core=0 endpt=1026 token=0 macAdd=01:00:5e:00:00:01 vlanId=65535 flowIdx=114,0
[MCU2_0]     51.975420 s: filterAddMacSharedCb: Address found: 1:0:5e:0:0:1
[MCU2_0]     51.981393 s: ETHFW: ADD_FILTER_MAC | S2C | status=0
[MCU2_0]     51.981513 s: ETHFW: ADD_FILTER_MAC | C2S | core=0 endpt=1026 token=0 macAdd=33:33:ff:24:6c:90 vlanId=65535 flowIdx=114,0
[MCU2_0]     51.987207 s: ETHFW: ADD_FILTER_MAC | S2C | status=0
[MCU2_0]     51.988175 s: ETHFW: ADD_FILTER_MAC | C2S | core=0 endpt=1026 token=0 macAdd=01:80:c2:00:00:00 vlanId=65535 flowIdx=114,0
[MCU2_0]     51.991037 s: Cpsw_periodicTick: dans=Cpsw_periodicTick =8
[MCU2_0]     51.991064 s: 
[MCU2_0]     51.991085 s: EnetPhy_tick: dans=EnetPhy_resetWaitState =1
[MCU2_0]     51.991107 s: 
[MCU2_0]     51.991183 s: Cpsw_periodicTick: dans=Cpsw_periodicTick =8
[MCU2_0]     51.991206 s: 
[MCU2_0]     51.991225 s: EnetPhy_tick: dans=EnetPhy_findingState =17
[MCU2_0]     51.991247 s: 
[MCU2_0]     51.991269 s: Cpsw_periodicTick: dans=Cpsw_periodicTick =8
[MCU2_0]     51.991290 s: 
[MCU2_0]     51.991308 s: EnetPhy_tick: dans=EnetPhy_findingState =18
[MCU2_0]     51.991329 s: 
[MCU2_0]     51.991347 s: Cpsw_periodicTick: dans=Cpsw_periodicTick =8
[MCU2_0]     51.991369 s: 
[MCU2_0]     51.991385 s: EnetPhy_tick: dans=EnetPhy_findingState =19
[MCU2_0]     51.991407 s: 
[MCU2_0]     51.991430 s: filterAddMacSharedCb: Address found: 1:80:c2:0:0:0
[MCU2_0]     51.997109 s: ETHFW: ADD_FILTER_MAC | S2C | status=0
[MCU2_0]     51.997362 s: ETHFW: ADD_FILTER_MAC | C2S | core=0 endpt=1026 token=0 macAdd=01:80:c2:00:00:03 vlanId=65535 flowIdx=114,0
[MCU2_0]     52.000190 s: filterAddMacSharedCb: Address found: 1:80:c2:0:0:3
[MCU2_0]     52.005839 s: ETHFW: ADD_FILTER_MAC | S2C | status=0
[MCU2_0]     52.005950 s: ETHFW: ADD_FILTER_MAC | C2S | core=0 endpt=1026 token=0 macAdd=01:80:c2:00:00:0e vlanId=65535 flowIdx=114,0
[MCU2_0]     52.005992 s: ETHFW: ADD_FILTER_MAC | S2C | status=0
[MCU2_0]     52.088680 s: Cpsw_periodicTick: dans=Cpsw_periodicTick =8
[MCU2_0]     52.088714 s: 
[MCU2_0]     52.088735 s: EnetPhy_tick: dans=EnetPhy_enableState =1
[MCU2_0]     52.088756 s: 
[MCU2_0]     52.088775 s: EnetPhy_enableState: dans=EnetPhy_enableState0 =1
[MCU2_0]     52.088798 s: 
[MCU2_0]     52.088826 s: EnetPhy_enableState: dans=EnetPhy_enableState1 =1
[MCU2_0]     52.088849 s: 
[MCU2_0]     52.089032 s: EnetPhy_enableState: dans=EnetPhy_enableState3 =64
[MCU2_0]     52.089057 s: 
[MCU2_0]     52.089075 s: EnetPhy_enableState: dans=EnetPhy_enableState4 =64
[MCU2_0]     52.089098 s: 
[MCU2_0]     52.089116 s: EnetPhy_enableState: dans=EnetPhy_enableState5 =94
[MCU2_0]     52.089139 s: 
[MCU2_0]     52.089157 s: EnetPhy_enableState: dans=EnetPhy_enableState6 =64
[MCU2_0]     52.089180 s: 
[MCU2_0]     52.089198 s: EnetPhy_enableState: dans=EnetPhy_enableState7 =64
[MCU2_0]     52.089221 s: 
[MCU2_0]     52.089298 s: EnetPhy_enableState: dans=EnetPhy_enableState8 =1
[MCU2_0]     52.089320 s: 
[MCU2_0]     52.089338 s: EnetPhy_enableState: dans=EnetPhy_enableState9 =0
[MCU2_0]     52.089360 s: 
[MCU2_0]     52.089830 s: EnetPhy_enableState: dans=loopbackEn
[MCU2_0]     52.089855 s: 
[MCU2_0]     52.089872 s: EnetPhy_enableState: dans=333333333333333
[MCU2_0]     52.089893 s: 
[MCU2_0]     52.089911 s: Cpsw_periodicTick: dans=Cpsw_periodicTick =8
[MCU2_0]     52.089932 s: 
[MCU2_0]     52.089949 s: EnetPhy_tick: dans=EnetPhy_findingState =17
[MCU2_0]     52.089971 s: 
[MCU2_0]     52.089992 s: Cpsw_periodicTick: dans=Cpsw_periodicTick =8
[MCU2_0]     52.090014 s: 
[MCU2_0]     52.090030 s: EnetPhy_tick: dans=EnetPhy_findingState =18
[MCU2_0]     52.090052 s: 
[MCU2_0]     52.090070 s: Cpsw_periodicTick: dans=Cpsw_periodicTick =8
[MCU2_0]     52.090091 s: 
[MCU2_0]     52.090108 s: EnetPhy_tick: dans=EnetPhy_findingState =19
[MCU2_0]     52.090129 s: 
[MCU2_0]     52.188677 s: Cpsw_periodicTick: dans=Cpsw_periodicTick =8
[MCU2_0]     52.188710 s: 
[MCU2_0]     52.188731 s: EnetPhy_tick: dans=EnetPhy_linkWaitState =1
[MCU2_0]     52.188753 s: 
[MCU2_0]     52.188823 s: EnetPhy_linkWaitState: dans=EnetPhy_linkWaitState =13
[MCU2_0]     52.188848 s: 
[MCU2_0]     52.188867 s: EnetPhy_linkWaitState: dans=EnetPhy_linkWaitState1 =13
[MCU2_0]     52.188891 s: 
[MCU2_0]     52.188911 s: EnetPhy_linkWaitState: dans=EnetPhy_linkWaitState4 =13
[MCU2_0]     52.188946 s: 
[   45.157033] ti_cpsw_proxy_client virtio2.ti.ethfw.ethdevice.-1.114: failed to receive response. Response Timedout
[   45.167290] ti_cpsw_proxy_client virtio2.ti.ethfw.ethdevice.-1.114: failed to add multicast mac filter err: -110
[   45.701030] ti_cpsw_proxy_client virtio2.ti.ethfw.ethdevice.-1.114: failed to receive response. Response Timedout
[   45.711274] ti_cpsw_proxy_client virtio2.ti.ethfw.ethdevice.-1.114: failed to add multicast mac filter err: -110

After executing this code(

  EnetPhy_setNextState(hPhy, ENETPHY_FSM_STATE_LINKED);

), the above error message will appear and the software will freeze.

static void EnetPhy_linkWaitState(EnetPhy_Handle hPhy)
{
    EnetPhy_State *state = &hPhy->state;
    uint32_t nwayCaps;
    uint16_t status;

    EnetPhy_readReg(hPhy, PHY_BMSR, &status);
    ENETTRACE_ERR(ENETPHY_SOK,"dans=EnetPhy_linkWaitState =%d\r\n", status);
    if ((status & BMSR_LINKSTS) != 0U)
    {
ENETTRACE_ERR(ENETPHY_SOK,"dans=EnetPhy_linkWaitState1 =%d\r\n", status);
        /* Populate FSM state now as most FSM states are bypassed for strapped PHYs */
        if (hPhy->phyCfg.isStrapped)
        {
            ENETTRACE_ERR(ENETPHY_SOK,"dans=EnetPhy_linkWaitState2 =%d\r\n", status);
            state->phyLinkCaps = EnetPhy_getLocalCaps(hPhy);
            nwayCaps = EnetPhy_findCommonNwayCaps(hPhy);
            if (nwayCaps != 0U)
            {
                ENETTRACE_ERR(ENETPHY_SOK,"dans=EnetPhy_linkWaitState3 =%d\r\n", status);
                EnetPhy_capToMode(nwayCaps, &state->speed, &state->duplexity);

                ENETTRACE_DBG("PHY %u: negotiated mode: %s",
                              hPhy->addr, EnetPhy_getModeString(state->speed, state->duplexity));
            }
        }
        ENETTRACE_ERR(ENETPHY_SOK,"dans=EnetPhy_linkWaitState4 =%d\r\n", status);
        EnetPhy_setNextState(hPhy, ENETPHY_FSM_STATE_LINKED);

Hi,

Can you please confirm, what changes you have made.

From logs it seems Link is Up from BMCR status value (13: 0x0D)

I suspect some assertion in Ethfw, so it is not responding for client requests.

Best Regards,
Sudheer

Hello, Sudheer：

could you please advise on using single native driver mode to configure SW9G SERDES1?

jin zhu said:

Hello, Sudheer：

could you please advise on using single native driver mode to configure SW9G SERDES1?

Do we need to start a new question post for this?

Hi,

jin zhu said:

could you please advise on using single native driver mode to configure SW9G SERDES1?

Do we need to start a new question post for this?

Yes, For Native Linux Driver enable for SGMII.

Doredla Sudheer Kumar said:

Yes, For Native Linux Driver enable for SGMII.

I have already mentioned it, link:e2e.ti.com/.../tda4vh-q1-how-to-enable-sgmii-for-native-linux-drivers

Hi,

jin zhu said:

I have already mentioned it, link:e2e.ti.com/.../tda4vh-q1-how-to-enable-sgmii-for-native-linux-drivers

Okay, will get response from Expert if you have any issues.
I have provided some E2E reference, Please proceed as per that.

May I know the status of SGMII from EthFw?

Best Regards,
Sudheer

Doredla Sudheer Kumar said:

May I know the status of SGMII from EthFw?

Hello, Sudheer：

The ethfw hierarchy should not need to be modified, as it should be compatible with SGMII. But now there is an error and no direction point.

Add, let me summarize this issue in RTOS:

1.When selecting to configure QSGMII(  app_ethfw_freertos.c file of function "appEthFwInit" change code :flags |= (ETHFW_BOARD_QENET_ENABLE | ETHFW_BOARD_SERDES_CONFIG);), the following error message appeared and was not resolved.

[MCU2_0]     52.188731 s: EnetPhy_tick: dans=EnetPhy_linkWaitState =1
[MCU2_0]     52.188753 s: 
[MCU2_0]     52.188823 s: EnetPhy_linkWaitState: dans=EnetPhy_linkWaitState =13
[MCU2_0]     52.188848 s: 
[MCU2_0]     52.188867 s: EnetPhy_linkWaitState: dans=EnetPhy_linkWaitState1 =13
[MCU2_0]     52.188891 s: 
[MCU2_0]     52.188911 s: EnetPhy_linkWaitState: dans=EnetPhy_linkWaitState4 =13
[MCU2_0]     52.188946 s: 
[   45.157033] ti_cpsw_proxy_client virtio2.ti.ethfw.ethdevice.-1.114: failed to receive response. Response Timedout
[   45.167290] ti_cpsw_proxy_client virtio2.ti.ethfw.ethdevice.-1.114: failed to add multicast mac filter err: -110
[   45.701030] ti_cpsw_proxy_client virtio2.ti.ethfw.ethdevice.-1.114: failed to receive response. Response Timedout
[   45.711274] ti_cpsw_proxy_client virtio2.ti.ethfw.ethdevice.-1.114: failed to add multicast mac filter err: -110

2.When selecting the initial configuration as SGMII(app_ethfw_freertos.c file of function "appEthFwInit" change code :flags |= (ETHFW_BOARD_ENET_BRIDGE_ENABLE | ETHFW_BOARD_SERDES_CONFIG);), the following error message appeared but was not resolved.

[MCU2_0]     51.077527 s: dans---MCM_GET_HANDLE
[MCU2_0]     51.077560 s: dans--EnetMcm: CPSW_9G on MAIN NAVSS
[MCU2_0]     51.087789 s: PHY 0 is alive
[MCU2_0]     51.087826 s: PHY 1 is alive
[MCU2_0]     51.087891 s: EnetPhy_initCfg: dans=EnetPhy_initCfg =0
[MCU2_0]     51.087915 s: 
[MCU2_0]     51.088084 s: CpswMacPort_setSgmiiInterface: MAC 1: SERDES PLL is not locked

3. I asked our FAE here, and he suggested handling this issue in Native Linux by modifying the device tree.

Overall, I feel that the debugging direction has fallen into a trap. Could you please tell me why it is so difficult to use SGMII1 to link the phy driver in CPSW9g. Can you provide a reference example based on the current SDK(9.01)?

Hi,

Both
ETHFW_BOARD_QENET_ENABLE & ETHFW_BOARD_ENET_BRIDGE_ENABLE are related to Board specific.
It will handle the PHY Reset & MAC Port configuration.

Other customer are using SGMII from EthFw, Refer below.
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1236114/tda4vh-q1-configure-sgmii-serdes

Best Regards,
Sudheer

Doredla Sudheer Kumar said:

Other customer are using SGMII from EthFw, Refer below.

According to the above link, all attempts have failed.

Do you have any official information to tell users that SDK can be used correctly?

Can you provide me with a patch for SGMII1 based on SDK configuration?

Thank you very much.

Hi,

jin zhu said:

Doredla Sudheer Kumar said:

Other customer are using SGMII from EthFw, Refer below.

According to the above link, all attempts have failed.

We have EthFw User Guide talks about Porting Guide for Board related info.
https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/09_00_01_01/exports/docs/ethfw/docs/user_guide/ethfw_c_porting_top.html

Please refer to once.

jin zhu said:

Can you provide me with a patch for SGMII1 based on SDK configuration?

We not have SGMII Phy to test on our side.
We can test only in ENET Bridge Mode for SGMII, instead of USXGMII. (Update port configuration to SGMII)
In EVM case we can just call SGMII SerDes configuration instead of USXGMII.

In your case also same, Apart from this you need to take care follow.
1. PHY Driver
2. MAC Port Configuration
3. SerDes clock configuration if using different SerDes (we have reference as per TI EVM, change SerDes instance)
4. SerDes configuration as per your connection (we have reference for SGMII, follow similar and change SerDes instance)
5. PHY reset related if you have any.

Best Regards,
Sudheer