[FAQ] TDA4VH-Q1: How to configure the Wave521CL VPU clock? (Linux)

Reference the Speed Grade table from Datasheet: 

The default clock on the Linux SDK are set with these ceiling values that round up to the nearest operating frequency based on the required frequency calculated by the Wave5 VPU driver. There are some modifications in these speed grade tables that are important to take note of.

J721s2:

• The above speed grade table represents the different grades and respective configurations for the TDA4(AL/VE/VL)
• The speed grade table dictates that the device type T, N, and H have clock limitations of 550MHz, 275MHz, and 275Mhz respectively. This is actually not a directly supported division in the driver and should be the following:
  • T: 600MHz (~523MP/s)
  • N: 300MHz (~261MP/s)
  • H: 300MHz (~261MP/s)

J784s4:

• The above speed grade table represents the different grades and respective configurations for the TDA4(VH/AH/AP/VP)
• The speed grade table dictates that all the device types and models of the TDA4xxxxT has a limited operating frequency of 550MHz. Like the J721s2, this is not a directly supported division and should be the following based on the supported use-cases for each model of the TDA4xxxxT:
  • TDA4VH88T: 600MHz (~523MP/s)
  • TDA4AH88T: 600MHz (~523MP/s)
  • TDA4VP88T: 300MHz (~261MP/s)
  • TDA4AP88T: 300MHz (~261MP/s)

How to configure the limit on the VPU clock?

Based on the device type and speed grade from the above information, you now need to configure your device's VPU clock to the associated value. This is done by deleting the default upper limit entries of the frequency operating table that is located in arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi or arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi depending on the device being used.

To set the VPU clock to have an upper limit of 300MHz, change the table to the following: 

To have these changes take effect, run make dtbs at the highest level of the linux kernel directory make the new device tree binary. Then copy arch/arm64/boot/dts/ti/k3-j784s4-evm.dtb or arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dtb to the root partition in /media/user/root/boot/dtb/ti.

On boot, the device's default is 600MHz. However, once you run an encode/decode process the changes will take effect and set the limit on the CODEC clock frequency.

How to verify the CODEC clock?

J721s2: 

The J72s1s2 only has a single instance of the VPU, therefore you only need to check one clock. This can be done by utilizing the k3conf tool with the following command:

• k3conf dump clock 179

J784s4: 

The J784s4 has two instances of the VPU, and therefore two clocks to verify. This can be done with the following command using the k3conf tool: 

• VPU0: k3conf dump clock 241
• VPU1: k3conf dump clock 242

By default since the 9.1 SDK the VPU has clock gating enabled to dynamically set the clock based on the current VPU operation. Therefore, when the VPU is not being used it will keep the clock running at 20MHz unless dictated otherwise by the frequency table in the device tree. This also means when verifying the clock with the k3conf dump clock commands, you will have to ssh to the board and run the command simultaneously as when the CODEC operation is happening.