AM6548: AM6548 SR2.0 - RTOS PDK ICSSG MII Support

Benjamin Roytburd

Part Number: AM6548

Tool/software:

Hello,

For the PDK RTOS code, and ICSSG firmware for the AM6548 IDK, does TI support using the ICSSGs in MII mode?

How would one go about doing this? In a design we have, so far I have modified the pinmux settings for MII mode with firmware I have written for RGMII on the IDKEVM. But our design with ICSSG0 MII + DP83848 does not seem to be working. The PHYs link up but ping tests seem to fail.

There also appears to be a discrepancy with the TI system configuration tool, for pr0_mii0 signals in the tool the RX/TX pins are mode 9/8, while in the generated C files the pins are mode 1/0. Why is that?

Thanks,
Ben

1 month ago

0 Benjamin Roytburd 1 month ago

Intellectual 260 points

Upon debugging, seems that MII RX is working, but MII TX is not. Seems to be a similar behavior to these threads:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1186430/tmdx654idkevm-no-tx-traffic-with-pru-icssg-on-mii-mode/4478618?tisearch=e2e-sitesearch&keymatch=icssg%2525252520mii#4478618
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/939934/am6548-where-to-find-pru-firmware-that-works-with-mii/3600414?tisearch=e2e-sitesearch&keymatch=DP83867IR#3600414

0 Nitika Verma 1 month ago in reply to Benjamin Roytburd

TI__Expert 4090 points

Hi Ben,

The ICSSG MII and RGMII TX pins are swapped in SoC integration. To get the MII TX working, correct programming of following registers is required:

Regards,

Nitika

0 Benjamin Roytburd 1 month ago in reply to Nitika Verma

Intellectual 260 points

Hi Nitka,

Thanks for the reply! I do not see those offsets in the AM6548 TRM, but I do see some similar settings here:

And the BSP code does appear to set the register correctly to account for that swap:

if (EnetMacPort_isRgmii(&cfg->mii))
{
    Icssg_wr32(hIcssg, baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_CFG_REGS_BASE + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_CFG_TXCFG0, 0x1803U);
    Icssg_wr32(hIcssg, baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_CFG_REGS_BASE + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_CFG_TXCFG1, 0x1903U);
}
else
{
    Icssg_wr32(hIcssg, baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_CFG_REGS_BASE + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_CFG_TXCFG0, 0x1903U);
    Icssg_wr32(hIcssg, baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_CFG_REGS_BASE + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_CFG_TXCFG1, 0x1803U);
}

This is from IcssgUtils_fwConfig in the PDK. And it appears to be setting TX_MUX_SEL0 to 1 for MII mode on the first port:

But I still do not see any transmit. Is there some setting I am missing perhaps? Like in the MMR register? Or elsewhere in the ICSSG peripheral?

Edit: Do I possibly need do download and configure the firmware for ICSSG0 port 2 as well? I have only configured port 1

Thanks,
Ben

0 Benjamin Roytburd 1 month ago in reply to Benjamin Roytburd

Intellectual 260 points

Ok, I believe we have resolved the issue. In our design we have PRG0_PRU1 transmit pins mapped to our MII transmit signals already:

So I actually believe we do not need to set TX_MUX_SEL0 in our code, and I will update the BSP accordingly.

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AM6548: AM6548 SR2.0 - RTOS PDK ICSSG MII Support