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Original question:

[FAQ] TMS320C6657: How to wake the second core by the first core in C6657 ? What is Boot-magic Address / Jump boot address...

TMS320C6657: After core 0 wake up the second Core, how to start SysBios (I meet task_creat faile problem, the error message shows heap Mem out of memory)

?? ?
Prodigy 40 points
Part Number: TMS320C6657
Other Parts Discussed in Thread: SYSBIOS

Tool/software:

Hi, dear TI engineer.

Problem describe:  I'm doing some SysBios project test: After core 0 wake Core1,  then creat a simple task to printf some words. But when followed the code step by step, the console shows me Task_creat fail and the HeapMem out of memory!!

Project info: I use ccs 9.3 creat a typical SYS/BIOS project, referenced Core 0 wake up the second core articles on TI forums:

[FAQ] TMS320C6657: How to wake the second core by the first core in C6657 ? What is Boot-magic Address / Jump boot address ? - Processors forum - Processors - TI E2E support forums

Keystone Bootloader Resources and FAQ (ti.com)  Section 4.14

Form these articles, I test core 0 wake up core 1 successully without SYS/BIOS.

But when I test in RTSC project, the problem appearing.

The test 1st step is core 0 wake up core core1, and creat a task, In the task diff core printf diff message.

Project Demo Pack :RTSC_MUTIPLE_BOOT.zip

RTSC part :mc2_c6657.zip

My doubt is whether my code logic is incorrect? Is there any demo project about mutiple core single image code ?

  • 0 in reply to Shankari G
    Prodigy 40 points

    Hi Shankari G,

    I have watched the IPC-SRIO example. The video showed,  you set 2 core in a group, and then core0 and core 1 both load program.

    But my actual application requirement is that only Core 0 need to download one images, core 1 no need to download image. Using this image wake up the second core. which means core 0 and core share the same code.

    What can I do base on IPC-SRIO example?

    Regards

  • 0 in reply to ?? ?
    TI__Mastermind 23425 points

    Dear Customer,

    1. IPC-SRIO example uses the SYSBIOS. 

    2. IPC-SRIO examples wakes up core 0 and core 1 

    ----

    [FAQ] TMS320C6657: How to wake the second core by the first core in C6657 ? What is Boot-magic Address / Jump boot address ? - Processors forum - Processors - TI E2E support forums

    Through this link, you achieved loading one single image in one of the cores and woke up the second core and executed the code by jumping into a program address.

    As a next step, refer the ( IPC SRIO-with sysBIOS ) and ( boot magic without SYSBIOS)  and try to integrate these two sets of code to achieve your custom requirement. 

    See, you can refer the examples given in the Processor SDK 6.3. It includes as many examples with SYSBIOS.

    Having these examples, after having a hands-on, you may have to come up with a software design ( HLD - High level design ) to accomplish your custom requirement.

    Providing a software design is beyond the scope of Forum support.

    Regards

    Shankari G

  • 0 in reply to Shankari G
    Prodigy 40 points

    Dear  Shankari G,

    Your answer coincides with the test I am currently conducting. I tested  ' ( IPC SRIO-with sysBIOS ) and ( boot magic without SYSBIOS) '. But one more important thing i have done is I changed the 'ti.platforms.evm6657'.

    The main change for the platforms.evm6657 is L2SAM  base address ( changed 0x00800000 -> 0x10800000(global address) ), and changed Memory Sections -> Code Memory selected: MSMCSRAM.

    After these changes core 0 can wake up the second core and no heap memory crash.

    PS: Is there a complete data sheet  explains the parameters in the SECTION group of the cmd file, such as fardata, Args, etc. Like text and stack is easy to understand, but I still have doubt about other parameters. I'm new in dsp, Please forgive my shallow knowledge.

    Thank you very much.

    Regards

  • 0 in reply to ?? ?
    TI__Mastermind 23425 points

    Dear Customer,

    That's good nice. Congrats.

    Sure, I can provide you the details on fardata and args etc.

    Please refer this doc: https://www.ti.com/lit/ug/spru187u/spru187u.pdf

    7.1.1 Sections


    The compiler produces relocatable blocks of code and data called sections. The sections are allocated
    into memory in a variety of ways to conform to a variety of system configurations. For more information
    about sections and allocating them, see the introductory object file information in the TMS320C6000
    Assembly Language Tools User's Guide.


    There are two basic types of sections:


    • Initialized sections contain data or executable code. The C/C++ compiler creates the following
    initialized sections:


    – The .args section contains the command argument for a host-based loader. This section is readonly. See the --arg_size option for details.
    – For EABI only, the .binit section contains boot time copy tables. For details on BINIT, see the
    TMS320C6000 Assembly Language Tools User's Guide for linker command file information.
    – For COFF ABI only, the .cinit section contains tables for initializing variables and constants.
    – The .pinit section for COFF ABI, or the .init_array section for EABI, contains the table for calling
    global constructor tables.
    – For EABI only, the .c6xabi.exidx section contains the index table for exception handling. The
    .c6xabi.extab section contains un-winded instructions for exception handling. These sections are
    read-only. See the --exceptions option for details.
    – The .name.load section contains the compressed image of section name. This section is readonly. See the TMS320C6000 Assembly Language Tools User's Guide for information on copy
    tables.
    – The .ppinfo section contains correlation tables and the .ppdata section contains data tables for
    compiler-based profiling. See the --gen_profile_info option for details.
    – The .const section contains string literals, floating-point constants, and data defined with the
    C/C++ qualifiers far and const (provided the constant is not also defined as volatile).
    – For EABI only, the .fardata section reserves space for non-const, initialized far global and static
    variables.
    – For EABI only, the .neardata section reserves space for non-const, initialized near global and
    static variables.
    – For EABI only, the .rodata section reserves space for const near global and static variables.
    – The .switch section contains jump tables for large switch statements.
    – The .text section contains all the executable code

    FOR MORE DETAILS

    Please refer this doc: https://www.ti.com/lit/ug/spru187u/spru187u.pdf

    Regards

    Shankari G