Tool/software:
How do we enable all eight(8) external ports of CPSW9G in TDA4VH using TI EVM?
TI EVM has a provision for connecting an ethernet expansion card QUAR enet card to 2 CPSW ports using two expansion connectors.
We can enable two MAC ports available to the expansion connectors as QSGMII main ports and the remaining ports as sub ports.
The QUAD expansion board is the same for both connectors and will conflict with PHY addresses mapped to the EMAC ports.
To avoid conflict with PHY addresses, we need to change the QUAD expansion card to use different PHY addresses.
Please refer to the QUAD expansion board User Guide and schematics for more information about how to configure the PHY addresses.
The following changes are to be considered to enable all 8 Ports of CPSW9G from TI EVM.
1. Make sure both Quad enet expansion cards have different PHY addresses.
2. Along with the above we need update enable the POWER & RESET signals for both QUAD ENET expansion cards as below.
a) For PHY reset add below in MDIO node at reset-gpios:
reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW> , <&exp2 20 GPIO_ACTIVE_LOW>;
b) For power on PHY add below in the exp2 node:
/* Power-up ENET2 EXPANDER PHY. */
qsgmii1-line-hog {
gpio-hog;
gpios = <9 GPIO_ACTIVE_HIGH>;
output-low;
};
3. Also, add SerDes lane configuration for both QUAD connectors.
As per TI EVM Port-7/Port-1 on Lane2 is available from the ENET1 expansion connector so either of one should be the master port, similarly Port-8/Port-2 on Lane3 is available from the ENET2 expansion connector so either of one should be the master port.
Among Port-1,2,3,4 one should be master and the rest will be sub ports.
Similarly, among Port-5,6,7,8 one should be master and the rest will be sub ports.
a) Please use the below configuration for the master ports definition:
&cpsw0_phy_gmii_sel{
ti,qsgmii-main-ports = <1>, <8>; //for Port1 & Port-8 Mater ports
//ti,qsgmii-main-ports = <2>, <7>; //for Port2 & Port-7 Mater ports
};
b) Please use the below SerDes Lane control configuration for IP selection as per master ports.
&serdes_ln_ctrl {
idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
<J784S4_SERDES0_LANE2_IP3_UNUSED>, <J784S4_SERDES0_LANE3_USB>,
<J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
<J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
<J784S4_SERDES2_LANE0_QSGMII_LANE5>, <J784S4_SERDES2_LANE1_QSGMII_LANE6>,
- <J784S4_SERDES2_LANE2_QSGMII_LANE7>, <J784S4_SERDES2_LANE3_QSGMII_LANE8>;
+ <J784S4_SERDES2_LANE2_QSGMII_LANE1>,<J784S4_SERDES2_LANE3_QSGMII_LANE8>; //for Port-1 Master and Port-8 Master
//+ <J784S4_SERDES2_LANE2_QSGMII_LANE7>,<J784S4_SERDES2_LANE3_QSGMII_LANE2>; //for Port-2 Master and Port-7 Master
};
4. Also, need to configure SerDes2 such that enable both Line2 (Port-1), Line3(Port-8) as follows.
&serdes2 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
serdes2_qsgmii_link: phy@0 {
reg = <2>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_QSGMII>;
resets = <&serdes_wiz2 3>, <&serdes_wiz2 4>;
};
};
// SPDX-License-Identifier: GPL-2.0
/**
* DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
* J7AHP board. The Add-On Ethernet Card has to be connected to ENET Expansion 1 slot on the
* board.
*
* Product Datasheet: https://www.ti.com/lit/ug/spruj74/spruj74.pdf
* Product Link: https://www.ti.com/tool/J721EXENETXPANEVM
*
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/phy/phy-cadence.h>
#include <dt-bindings/phy/phy.h>
#include "k3-pinctrl.h"
&{/} {
aliases {
ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@5";
ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@6";
ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@7";
ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@8";
ethernet5 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
ethernet6 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
ethernet7 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
ethernet8 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
};
};
&main_cpsw0 {
status = "okay";
};
&main_cpsw0_port1 {
status = "okay";
phy-handle = <&cpsw9g_phy5>;
phy-mode = "qsgmii";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 1>, <&serdes2_qsgmii_link>;
phy-names = "mac", "serdes";
};
&main_cpsw0_port2 {
status = "okay";
phy-handle = <&cpsw9g_phy6>;
phy-mode = "qsgmii";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 2>, <&serdes2_qsgmii_link>;
phy-names = "mac", "serdes";
};
&main_cpsw0_port3 {
status = "okay";
phy-handle = <&cpsw9g_phy4>;
phy-mode = "qsgmii";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 3>, <&serdes2_qsgmii_link>;
phy-names = "mac", "serdes";
};
&main_cpsw0_port4 {
status = "okay";
phy-handle = <&cpsw9g_phy7>;
phy-mode = "qsgmii";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 4>, <&serdes2_qsgmii_link>;
phy-names = "mac", "serdes";
};
&main_cpsw0_port5 {
status = "okay";
phy-handle = <&cpsw9g_phy1>;
phy-mode = "qsgmii";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_qsgmii_link>;
phy-names = "mac", "serdes";
};
&main_cpsw0_port6 {
status = "okay";
phy-handle = <&cpsw9g_phy2>;
phy-mode = "qsgmii";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 6>, <&serdes2_qsgmii_link>;
phy-names = "mac", "serdes";
};
&main_cpsw0_port7 {
status = "okay";
phy-handle = <&cpsw9g_phy0>;
phy-mode = "qsgmii";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 7>, <&serdes2_qsgmii_link>;
phy-names = "mac", "serdes";
};
&main_cpsw0_port8 {
status = "okay";
phy-handle = <&cpsw9g_phy3>;
phy-mode = "qsgmii";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 8>, <&serdes2_qsgmii_link>;
phy-names = "mac", "serdes";
};
&cpsw0_phy_gmii_sel {
ti,qsgmii-main-ports = <1>, <8>; //for Port1 & Port-8 Mater ports
};
&main_cpsw0_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mdio0_pins_default>;
bus_freq = <1000000>;
reset-gpios = <&exp2 20 GPIO_ACTIVE_LOW>, <&exp2 17 GPIO_ACTIVE_LOW>;
reset-post-delay-us = <120000>;
#address-cells = <1>;
#size-cells = <0>;
cpsw9g_phy0: ethernet-phy@16 {
reg = <16>;
};
cpsw9g_phy1: ethernet-phy@17 {
reg = <17>;
};
cpsw9g_phy2: ethernet-phy@18 {
reg = <18>;
};
cpsw9g_phy3: ethernet-phy@19 {
reg = <19>;
};
cpsw9g_phy4: ethernet-phy@24 {
reg = <24>;
};
cpsw9g_phy5: ethernet-phy@25 {
reg = <25>;
};
cpsw9g_phy6: ethernet-phy@26 {
reg = <26>;
};
cpsw9g_phy7: ethernet-phy@27 {
reg = <27>;
};
};
&exp2 {
/* Power-up ENET1 EXPANDER PHY. */
qsgmii1-line-hog {
gpio-hog;
gpios = <9 GPIO_ACTIVE_HIGH>;
output-low;
};
/* Power-up ENET1 EXPANDER PHY. */
qsgmii-line-hog {
gpio-hog;
gpios = <16 GPIO_ACTIVE_HIGH>;
output-low;
};
/* Toggle MUX2 for MDIO lines */
mux-sel-hog {
gpio-hog;
gpios = <13 GPIO_ACTIVE_HIGH>, <14 GPIO_ACTIVE_HIGH>, <15 GPIO_ACTIVE_HIGH>;
output-high;
};
};
&main_pmx0 {
mdio0_pins_default: mdio0-pins-default {
pinctrl-single,pins = <
J784S4_IOPAD(0x05c, PIN_INPUT, 4) /* (AC36) MCASP2_AXR0.MDIO1_MDIO */
J784S4_IOPAD(0x058, PIN_INPUT, 4) /* (AE37) MCASP2_AFSX.MDIO1_MDC */
>;
};
};
&serdes_ln_ctrl {
idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
<J784S4_SERDES0_LANE2_IP3_UNUSED>, <J784S4_SERDES0_LANE3_USB>,
<J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
<J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
<J784S4_SERDES2_LANE0_QSGMII_LANE5>, <J784S4_SERDES2_LANE1_QSGMII_LANE6>,
<J784S4_SERDES2_LANE2_QSGMII_LANE1>,<J784S4_SERDES2_LANE3_QSGMII_LANE8>; //for Port-1 Master and Port-8 Master
};
&serdes_wiz2 {
status = "okay";
};
&serdes2 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
serdes2_qsgmii_link: phy@0 {
reg = <2>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_QSGMII>;
resets = <&serdes_wiz2 3>, <&serdes_wiz2 4>;
};
};Note:
Also, make sure that “k3-j784s4-evm-virt-mac-client.dtbo“ is not added to the overlay and EthFw is not loaded on MCU2_0
Above changes will be for Native Linux Driver for CPSW9G.
If you are using ETHFW, enable Expansion power reset from u-boot and configure the CPSW Ports & SerDes from EthFw.