• State Resolved
  • Locked Locked
  • Replies 8 replies
  • Answers 1 answer
  • Subscribers 102 subscribers
  • Views 145 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM5716: PHY initialization works, but cannot ping on custom board

Vikesh Subramanian
Prodigy 80 points
Part Number: AM5716

Tool/software:

Hello,

We are bringing up a custom board and trying to configure the cpsw ethernet. There is a single PHY with address 2 connected to RGMII0. I am able to run the loopback test successfully after changing the address defined in emac_soc.c, but I cannot get the NIMU examples working. The board successfully negotiates a connection, but there is no ping. Do you have any insights into this issue?

Thank you,

Vikesh

  • 0
    TI__Guru* 87085 points

    Hi VIkesh,

    What SDK and HLOS are you using?

    regards

    Suman

  • 0 in reply to Suman Anna
    Prodigy 80 points

    Hello Suman,

    We are using TI-RTOS version 06_03_02_08 running NDK version 03_61_01_01

    Best,

    Vikesh

  • 0 in reply to Vikesh Subramanian
    TI__Mastermind 27290 points

    Hi Vikesh,

    Can you probe the phy registers from the application to see if the link is up?

    Have you also tried the phy loopback test? If not can you give this a try.

    Regards,
    Tanmay

  • 0 in reply to Tanmay Patil
    Prodigy 80 points

    Hi Tanmay,

    I have run the loopback test successfully and the registers indicate the link is up.

    Thanks,

    Vikesh

  • 0 in reply to Vikesh Subramanian
    TI__Mastermind 27290 points

    Hi Vikesh,

    Can you please provide the following details:

    • Can you share the name of the example you are using and the changes you have made in that if any.
    • Can you also share whatever logs you see from the application.
    • Is the ping done from SOC to external or from external to SoC?
    • Can you see the ARP packets being trandmitted/received in NDK?

    Regards,
    Tanmay

  • 0 in reply to Tanmay Patil
    Prodigy 80 points

    Hello Tanmay,

    Thanks for the help. I am running NIMU_BasicExample_idkAM571x_armExampleproject. The output we see is shown below. I am pinging from a laptop to the SoC. I have modified emac_soc.c and rebuilt PDK to change PHY addresses (we have nothing connected to RGMII1 and have a PHY with address 2 connected to RGMII0). I have also changed the cfg file to use our custom board library. Apart from this there are no modifications to the example.

  • 0 in reply to Vikesh Subramanian
    TI__Mastermind 27290 points

    Hi Vikesh,

    The reg dump all flag align error. This means that there might be some issue with the delay in RGMII link. Can you re-check the delay setting for the MAC and the phy again. Correcting this will most likely resolve the issue.

    Regards,
    Tanmay

  • +1 in reply to Tanmay Patil
    Prodigy 80 points

    Hi Tanmay,

    After looking at the delay settings I think there is a bug in the idkAM571x board library which we based our code on. In order to write delay registers, access needs to be unlocked by writing 0xAAAA to iodelay module CONFIG_REG_8. Line 176 in iodelay_config.c attempts to do this with the CSL_FINS macro:

    CSL_FINS(ioDelayCfg->CONFIG_REG_8, IODELAYCONFIG_CONFIG_REG_8_GLOBAL_LOCK_BIT,
             CONFIG_REG_8_UNLOCK_GLOBAL_LOCK);

    This expands to the following:

    ((ioDelayCfg->CONFIG_REG_8) = ((ioDelayCfg->CONFIG_REG_8) & ~0x00000001U) | (((0x0000AAAAU) << 0U) & 0x00000001U))

    Therefore this line attempts to write 0 to the least significant bit of CONFIG_REG_8, which is insufficient to unlock delay registers. This means delay calibration does not happen successfully. Changing this line to the following solved my problem.

    ioDelayCfg->CONFIG_REG_8 = CONFIG_REG_8_UNLOCK_GLOBAL_LOCK;