[FAQ] AM3351 , AM3352 , AM3354 , AM3356 , AM3357 , AM3358 , AM3359 Custom board design – E2E and FAQ references to Get started

Hi Board designers,

Refer below FAQ related to AM335x clock:

(19) AM3358: Absolute maximum ratings for XTAILIN (OSC0) input - Processors forum - Processors - TI E2E support forums

OSC0 input is powered from the VDDS_OSC power rail, which is 1.8V. Absolute maximum input voltage for this input is VDDS_OSC +0.3V. Absolute minimum is -0.5V. It's important to note that no external voltage should be applied to OSC0 pin before the VDDS_OSC supply has fully ramped-up and stabilized. This means that you should either use an external oscillator powered from VDDS_OSC, or place an external 1.8V buffer powered from VDDS_OSC.

(19) AM3358-EP: Overdriving oscillator input - Processors forum - Processors - TI E2E support forums

(19) AM3358: OSC0 crystal requirements - Processors forum - Processors - TI E2E support forums

(19) AM3358: Frequency accuracy - Processors forum - Processors - TI E2E support forums

Crystals are defined to have an initial frequency accuracy at room temperature. They should also provide another parameter that defines frequency deviation due to temperature change relative to room temperature. They typically provide another parameter that defines a frequency change due to aging.

You must combine all three contributors of frequency error to determine the maximum frequency deviation expected across operating conditions for the life of the product.

I have included a couple of links to crystal datasheets that you can use as examples.

ABM11W-25.0000MHZ-8-D1X-T3: https://abracon.com/Resonators/ABM11W.pdf

ABM10W-25.0000MHZ-8-D1X-T3: https://abracon.com/Resonators/ABM10W.pdf

Keep in mind the crystal doesn't dissipate much power, so there is no significant self-heating. The operating temperature of the crystal is typically the same temperature as the PCB board. Therefore, a crystal rated for 85 degrees Celsius may be good enough for most applications.

(19) AM3358: Am3358 - Processors forum - Processors - TI E2E support forums

The RTC logic in AM335x does not play any role in the various low-power sleep states support by AM335x while power remains on. These low-power sleep states are defined by software, where clocks are stopped for some logic functions and clock frequency reduced for other logic functions. You need to research the various modes supported by your operating system.

The Power Estimator Tool is the best way to understand current consumption based on your specific use case.

The RTC drift will be a function of the crystal circuit you connect to the RTC oscillator. In a typical application the RTC is constantly updated by the processor operating system while it has power, which gets its time from a accurate on-line time source. The RTC only needs to keep time while the processor is turned off. The off-time is typically short relative the time it takes for the drift to be a concern. The RTC will be updated by the operating system again after it turns on the PMIC, the processor boots the operating system, and it gets access to an accurate on-line time source.

Based on your questions, you have not read the TRM or researched what is supported by software. I will not be able to talk you through all of these details. You need to research your options.

(19) AM3358: AM335x OSC0 Crystal Circuit Load Capacitance - Processors forum - Processors - TI E2E support forums

The crystal shunt capacitance is in parallel with the series combination of C1 and C2. If the crystal requires a load of 18pf to oscillate at the correct frequency, the formula is saying you subtract the crystal shunt capacitance from the load it expects to determine what external capacitive load needs to be added to reach a load of 18pf. In this case it would be 18pF - 5pf = 13pf. Assuming your PCB traces have zero capacitance, the values for C1 and C2 would need to be 26pf. However, there is a good chance your PCB has 2pf to 3pf of capacitance on each signal trace. You would need to subtract that from the calculated value of 26pf and select a value like 24pf for C1 and C2.

The datasheet limits are for the combination of the external capacitor plus your PCB trace capacitance. Therefore, a crystal that requires 18pf of load would not be a good choice for this device.

I'm not sure why the boards you mentioned were designed to use a crystal that requires a load of 18pf. I suspect the TI board was designed before the oscillator limits were defined and the BeagleBone board simply followed the example and used the same crystal. I would not recommend following their example by selecting a crystal that operates outside of the limits defined by the datasheet. 

(+) AM3358: clipped sine wave for XTALIN/OSC0_IN? - Processors forum - Processors - TI E2E support forums

It is not unusual to find the crystal circuit producing a clipped sinusoid waveform on the oscillator XTALIN. The oscillator will produce a reference clock as long as the signal swing on XTALIN exceeds the Vih min and Vil max values defined in the Electrical Characteristics table of the AM335x datasheet. However, the slow changing sinusoid signal can be problematic in a system with lots of electrical noise. 

The slow voltage change of a sinusoid signal makes it easier for electrical noise to couple into the crystal circuit and produce a non-monatomic transition just as the signal crosses the input buffer switching threshold. If the noise source induces enough potential, the non-monatomic event my exceed the hysteresis of the input buffer which causes it to produces a glitch on the internal reference clock. Several customers using AM335x have experienced this issue, where the glitch commonly causes a timer operating from the oscillator clock to suddenly jump forward or backwards in time. The glitch effectively over-clocks the timer logic circuits which causes it to do unpredictable things. This glitch has occasionally caused other issues like the PLL suddenly changing its operating frequency.

I agree radiated emissions from a sinusoid signal are much easier to resolve than emissions from a square wave signal. However, radiated noise can be minimized if your system design implements a high-quality power distribution network and all of the your signal paths have controlled impedance paths with minimum loop inductance. Typically if you minimize radiated emissions, the self induced noise may be acceptable for using a sinusoid source for XTALIN. However, some applications place a system in a noisy electrical environment where it would not be wise to use a sinusoid source. If this is the case, you may need to perform noise immunity testing for your product to understand its susceptibility to external noise sources.

(+) AM3358: Frequency tolerance and frequency stability of 24Mhz Crystal - Processors forum - Processors - TI E2E support forums

The accuracy of the AM335x reference clock source should be based on system level requirements. For example, you may need a 30 PPM reference clock if an AM335x timer is being used to operate something that needs this level of accuracy. 

The 50 PPM limit was defined for AM335x because the RMII Ethernet standard requires this accuracy. The other Ethernet standards only require 100 PPM, so you may be able to back-off on this 50 PPM requirement if not using RMII. However, this depends if you have other system function that require an accuracy of 50 PPM. I would not recommend going above 100 PPM as this may begin to effect other peripheral interfaces.

Keep in mind, a crystal has three contributions to accuracy. There is a parameter that defines initial accuracy, another parameter that defines accuracy over operating temperature, and aging parameter that defines how much the resonate frequency changes over time due to aging effects. When selecting a crystal, you must combine all of these to determine frequency accuracy across all operating conditions for the life of the product.

Reliable start-up is also a concern with crystal selection. The max ESR of the crystal is one of the primary concerns. The AM335x oscillator may not have enough gain to reliably start oscillation if the crystal ESR is too low. Many crystal datasheets define a worst case max ESR value for the entire family of crystals rather than a specific max ESR for the crystal being selected. In most cases the higher frequency crystals in the family will have a much lower max ESR value that what is found in the datasheet. Therefore, you may need to contact the crystal manufacture and request a device specific datasheet for the crystal part number you plan to use.

One way to confirm you have start-up margin, is by inserting a resistor in series with the selected crystal and checking for reliable start-up across all operating conditions. I suggest you begin with a resistor value that is about 5x the max ESR of the crystal. If you have start-up issues with this value you can reduce it to 3x. There is not enough gain margin if oscillation will not reliably start with a 3x resistor. You would need to select a crystal with lower ESR if you find it will not reliably start with a 3X series resistor.

(+) AM3358: RTC CLK_32KHz From PLL accuracy - Processors forum - Processors - TI E2E support forums

Using a 1.8V LVCMOS 32.768kHz oscillator should resolve the issue if it is caused by noise coupling into the crystal circuit.  They could easily prove this is the case by removing crystal components and modifying a few systems to source the RTC from an external 32.768kHz LVCMOS source.

(+) AM3358: RTC crystal does not work - Processors forum - Processors - TI E2E support forums

The RTC oscillator is disabled by default at reset release time. See section 20.3.5.19 of the AM335x TRM Rev. P.

(+) AM3358: Generate a 32.768 KHz clock from processor at a GPIO - Processors forum - Processors - TI E2E support forums

AM335x has two internal 32.768KHz clock sources.

The first is named CLK_32KHZ. This source originates from a fractional divider sourced from the peripheral PLL. There is no way to route this clock to any of the device pins.

The second is an optional clock named CLK_32K_RTC. This source originates from the 32K crystal oscillator (OSC1) and has the option of being routed to the CLKOUT2 signal which can be multiplexed to the device XDMA_EVENT_INTR1 pin.

Note: OSC1 has been problematic for some products. It may be easy for noise to couple into the crystal circuit and generate glitches on OSC1's clock output as the slow changing crystal signal crosses the threshold of the input buffer.

(+) AM3358: MCASP Clock Generation - Processors forum - Processors - TI E2E support forums

(+) AM3358: Custom board bring up issue - Processors forum - Processors - TI E2E support forums

(+) AM3358: Custom board bringup - Processors forum - Processors - TI E2E support forums

(+) AM3358-EP: Clock Symmetry - Space & High Reliability Forum (Read Only) - Space & High Reliability (Read Only) - TI E2E support forums

As we usually use oscillators with 40:60 waveform symmetry I have been asked to determine if this is a general requirement (to allow correct operation of the PLLs for example) or driven by any specific interface on the device.

This is a timing constraint that is applied during the design of the processor. It defines the timing assumptions used for timing closure. Exceeding this input specification invalidates the timing closure.

(+) AM335x OSC0 crystal series resistance effect to oscillator stable startup - INT- Processors Forum (Read-Only) - INT- Processors (Read-Only) - TI E2E support forums

Can you ask the customer to provide the electrical parameters of the crystal and schematic of the crystal circuit they plan to use?

The data sheet defines a maximum ESR value of 48 ohms for a 24MHz crystal. This is approximately 1/3 of 144 ohms which is the worst case negative resistance of the oscillator and about 1/5 of 240 ohms which is the nominal negative resistance of the oscillator. This assume a Rd value of zero ohms.

Our recommended crystal circuit shows an optional series damping resistor (Rd) inserted between the oscillator output and the resonant crystal circuit. This damping resistor is used to reduce drive level of the feedback signal that maintains oscillation which will reduce power dissipation of the crystal.

The data sheet provides a formula for calculating crystal power dissipation. This formula assumes the damping resistor (Rd) value is zero ohms. If the customer determines the power dissipation of the crystal is too high using this formula, they may need to increase the value of Rd. Once they increase the value of Rd, they need to measure voltage across the crystal and replace VDDS_OSC in the power dissipation formula with the measured voltage to determine power dissipation of the crystal. They may need to adjust the value of Rd and repeat the measurement until the optimum value of Rd that maintains safe power dissipation in the crystal has been determined.

Once they have determined the correct value of Rd that is required to maintain safe power dissipation in the crystal, the gain margin required for the oscillator to start can be determined by temporarily inserting a resistor in series with the crystal. The value of this resistor can be increased from zero ohms while operating the product across all expected environmental conditions until the oscillator will no longer start oscillating. The ratio of this resistor value plus the ESR of the crystal divided by the ESR of the crystal represents the gain margin of the oscillator with damping resistor Rd installed.

This crystal has a maximum ESR greater then the vlaue recommended in the data sheet, so they will need to perform the tests described in my previous reply to confirm this crystal allows the system to have enough gain margin for their product.

(+) AM335x and DDR3 termination - Processors forum - Processors - TI E2E support forums

Regards,

Sreenivaa