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Problems/Questions for Interrupt triggered by EDMA completion on C6678

Dongning Li
Intellectual 860 points
Other Parts Discussed in Thread: SYSBIOS

I encountered some problems with EDMA completion interrupt, which was reported in my posting below:

http://e2e.ti.com/support/embedded/f/355/p/137259/497771.aspx#497771

 Instead of continuing that thread for my new findings, I create this new thread for my findings/problems/questions as below. In all my examples, I uses sysbios CpIntc for interrupt and shadow region for my Edma channels. Futhermore, for the log below, edmaId (0, 1, or 2) is Edma controller index, and m_intcId (0, or 1) is the interrupt controller index. I also uses "//" at the end of some log lines to provide my comments. Now the problems/questions:

1.       If I uses different host interrupts which maps to the same primary event, then I will get E_unpluggedSysInt error. The following shows the trace:

[C66xx_0] edmaId(1), m_intcId(0): m_sysInt(8) => m_hostInt(32)

[C66xx_1] edmaId(1), m_intcId(0): m_sysInt(9) => m_hostInt(43)

[C66xx_0] dstMsg(0082ca58), m_dspSeqNum(0), m_sysInt(8) // Here an Edma transfer request is issued.

[C66xx_0] CTraceQ::TraceEdmaCompleted() – 1 core0 // Edma transfer is completed.

[C66xx_1] ti.sysbios.family.c66.tci66xx.CpIntc: line 311: E_unpluggedSysInt: System Interrupt# 0 is unplugged

ti.sysbios.gates.GateMutex: line 97: assertion failure: A_badContext: bad calling context. See GateMutex API doc for details.

[C66xx_1] xdc.runtime.Error.raise: terminating execution

I do not have the this problem if host interrupts are mapped to different primary events.  Can anyone tell me why Edma and sysbios CpIntc behaves like this? Is this an Edma or Bios problem? If not, does this means that one should never use host interrupts mapped to the same primary event?

2.       For cores 0 to 3, if I have each core setup to use Edma completion interrupt and setup the CpIntc accordingly, an EDMA completion from one core will trigger interrupt for all other cores. Here the other cores issued no Edma request. The same applies to cores 4 to 7 using the 2nd CpIntc. The following traces show this problem:

[C66xx_7] edmaId(1), m_intcId(1): m_sysInt(15) => m_hostInt(72)

[C66xx_1] edmaId(0), m_intcId(0): m_sysInt(39) => m_hostInt(44)

[C66xx_0] edmaId(0), m_intcId(0): m_sysInt(38) => m_hostInt(32)

[C66xx_2] edmaId(0), m_intcId(0): m_sysInt(40) => m_hostInt(56)

[C66xx_3] edmaId(0), m_intcId(0): m_sysInt(41) => m_hostInt(68)

[C66xx_4] edmaId(1), m_intcId(1): m_sysInt(12) => m_hostInt(36)

[C66xx_5] edmaId(1), m_intcId(1): m_sysInt(13) => m_hostInt(48)

[C66xx_6] edmaId(1), m_intcId(1): m_sysInt(14) => m_hostInt(60)

[C66xx_0] dstMsg(0082c918), m_dspSeqNum(0), m_sysInt(38) // issue Edma request

[C66xx_2] CTraceQ::TraceEdmaCompleted() - 1 core2

[C66xx_3] CTraceQ::TraceEdmaCompleted() - 1 core3

[C66xx_0] CTraceQ::TraceEdmaCompleted() - 1 core0

[C66xx_1] CTraceQ::TraceEdmaCompleted() - 1 core1

[C66xx_4] dstMsg(0082cd18), m_dspSeqNum(0), m_sysInt(12) // issue Edma request

[C66xx_5] CTraceQ::TraceEdmaCompleted() - 1 core5

[C66xx_6] CTraceQ::TraceEdmaCompleted() - 1 core6

[C66xx_7] CTraceQ::TraceEdmaCompleted() - 1 core7

[C66xx_4] CTraceQ::TraceEdmaCompleted() - 1 core4

I thought that each completion should only triggers its own interrupt. Each core uses its own Edma channel, own system int, own host int and own hwi. The mapping between host int and hwi is done in cfg script as below:

CpIntc.mapHostIntToHwiMeta(32 + 11*0 + 0, 4 + 0);
CpIntc.mapHostIntToHwiMeta(32 + 11*1 + 1, 4 + 8);
CpIntc.mapHostIntToHwiMeta(32 + 11*2 + 2, 4 + 2);
CpIntc.mapHostIntToHwiMeta(32 + 11*3 + 3, 4 + 3);
CpIntc.mapHostIntToHwiMeta(32 + 11*0 + 4, 4 + 4);
CpIntc.mapHostIntToHwiMeta(32 + 11*1 + 5, 4 + 5);
CpIntc.mapHostIntToHwiMeta(32 + 11*2 + 6, 4 + 6);
CpIntc.mapHostIntToHwiMeta(32 + 11*3 + 7, 4 + 7);

Can anyone tell me why one Edma completion system interrup trigers other interrupts?

 

3.       If core4 using the third Edma controller and the following settings, the Edma completion causes E_stackOverflow erro even if only this core is doing usefule work, while the other cores are just sleeping. I do not have this problem if this core uses the 2nd Edma controller. Can anyone tell me why or can reproduce this problem?

Channel number: 5

Parameter number: 5

Que number: 0

Region number: 4

Hwi: 6

[C66xx_4] edmaId(2), m_intcId(1): m_sysInt(28) => m_hostInt(36)

[C66xx_4] ti.sysbios.knl.Task: line 334: E_stackOverflow: Task 0x1 stack overflow.

[C66xx_4] xdc.runtime.Error.raise: terminating execution

 

 

 Dongning

 

  • 0
    TI__Mastermind 18320 points

    Dongning,

    We're out of ideas on how to further help you from the BIOS side, and this latest query seems to be EDMA specific.  I am moving this thread to the C66x device forum in hopes that you will get a faster resolution there...

    Dave

  • 0
    Intellectual 860 points

    Regardging the 3rd problem described above, I find that powering off, then on will typically make it work. Hard reset normally does no work. Once it is working after a power reset, I can repeat load/run/stop cycle without any error. Interrupt triggered by core0 to core3 works more consistently. I am using TMDXEVL6678L emulator.

    Dongning

  • 0 in reply to Dongning Li
    Intellectual 860 points

    I have further findings while discussing related issue in the following thread:

    http://e2e.ti.com/support/embedded/f/355/p/137206/519392.aspx#519392

    Herewith I attach the project code again.

    7585.TestTrace20111101.zip

    Here is a brief description, but the details can be found in the above thread. The code setups core 0, 1, 2 and 3 for using EDMA shadow region 0, 1, 2 and 3 respectively. The associated EDMA channels respectively use completion codes 8, 9, 10 and 11. After the setup, only core0 issue an EDMA request. However, its completion triggers 5 EDMA transfer completion system interrupts, 4 for shadow region and one for global. However, EDMA's IPR/IPRH shows that only one interrupt pending. I just do not understand how one EDMA transfer completion could cause 5 EDMA transfer completion system interrupts?

    The EDMA channel is setup with

        CSL_EDMA3_ITCCH_DIS,

        CSL_EDMA3_TCCH_DIS,

        CSL_EDMA3_ITCINT_DIS,

    and no linking.

     

    When running the code, it generates the following log:

     [C66xx_0] edmaId(1), m_intcId(0): m_sysInt(8) => m_hostInt(32)

     [C66xx_1] edmaId(1), m_intcId(0): m_sysInt(9) => m_hostInt(44)

     [C66xx_2] edmaId(1), m_intcId(0): m_sysInt(10) => m_hostInt(56)

     [C66xx_3] edmaId(1), m_intcId(0): m_sysInt(11) => m_hostInt(68)

     [C66xx_0] evt(21), host(32), hwi(4)

     [C66xx_1] evt(22), host(44), hwi(12)

     [C66xx_2] evt(23), host(56), hwi(6)

     [C66xx_3] evt(24), host(68), hwi(7)

     [C66xx_0] rawStatus(00000000), eventFlag(0000800d), enableReg(00000f00)

     [C66xx_0] dstMsg(0082d080), m_dspSeqNum(0), m_sysInt(8)

     [C66xx_0] CTraceQ::TraceEdmaCompleted() - 0 core0, IPR(00000000 00000100)

     [C66xx_1] rawStatus(00000000), eventFlag(0000000c), enableReg(00000f00)

     [C66xx_2] rawStatus(00000000), eventFlag(0000000c), enableReg(00000f00)

     [C66xx_3] rawStatus(00000000), eventFlag(0000000c), enableReg(00000f00)

     [C66xx_1] CTraceQ::TraceEdmaCompleted() - 0 core1, IPR(00000000 00000100)

     [C66xx_2] CTraceQ::TraceEdmaCompleted() - 0 core2, IPR(00000000 00000100)

     [C66xx_3] CTraceQ::TraceEdmaCompleted() - 0 core3, IPR(00000000 00000100)

     [C66xx_0] iFlags(00000001), hostIntFlags(00000001), rawStatus(00000f40), eventFlag(0020800d), enableReg(00000f00)

     [C66xx_2] iFlags(00000004), hostIntFlags(00000004), rawStatus(00000f40), eventFlag(0080000d), enableReg(00000f00)

     [C66xx_3] iFlags(00000008), hostIntFlags(00000008), rawStatus(00000f40), eventFlag(0100000d), enableReg(00000f00)

     [C66xx_1] iFlags(00000002), hostIntFlags(00000002), rawStatus(00000f40), eventFlag(0040000d), enableReg(00000f00)

     

    In the code I use my own dispatch CpIntc_dispatch_(), which does not clear system interrupts to show what system interrupts have happened.

     

    Anyone can explain why one EDMA transfer completion triggered five EDMA transfer completion system interrupts?

     

    Dongning

     

  • 0 in reply to Dongning Li
    TI__Genius 12065 points

    Dongning,

    In your source code, it looks like you enable every channel in every shadow region.

        if (instNum == 0)
        {
          /* YES. DRAE enable(Bits 0-15) for the shadow region; since there are 16 channels. */
          regionAccess.drae   = 0xFFFF;
          regionAccess.draeh  = 0x0;
        }
        else
        {
          /* YES. DRAE enable(Bits 0-63) for the shadow region; since there are 64 channels. */
          regionAccess.drae   = 0xFFFFFFFF;
          regionAccess.draeh  = 0xFFFFFFFF;
        }

    It will cause problem that one transfer completion will generate the interrupts to all the shadow regions. You can try to not overlap the channel allocation and transfer completion code among the shadow regions.

    Please refer to the A.2 Miscellaneous Programming in the EDMA user guide.

    Hope it can solve your interrupt issue.

    Sincerely,

    Steven

     

  • 0 in reply to Steven Ji
    Intellectual 860 points

    Hi Steven,

    Thank you very much for your reply.

    Using the same number for completion code and the channel number and then set the corresponding bit in DRAE solves my problem. I noticed that if the channel number and the completion code are different, then setting the DRAE bit to either of them fails generate interrupt. But I can always use the same value for both, so it is not an issue for me.

    Dongning