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Original question:
TDA4VE-Q1: Problems with creating and starting the tda4ve ubi burning file system
Tool/software:
hello teams:
sdk update from sdk805 to sdk902
target sdk version: 09.02.00.05 tisdk-tiny-image-j721s2-evm.tar.xz
hw: tda4ve
sbl boot stuck for a while at
SCISERVER Board Configuration header population... PASSED
Sciclient_setBoardConfigHeader... PASSED
01000000011a00006a3761657000000000000000475020200100010001000100CCCSBL Revision: 01.00.10.01 (Jul 25 2024 - 17:04:55) 306 main (Jul 25 2024 - 17:04:55) 320 main (Jul 25 2024 - 17:04:55) 329 main (Jul 25 2024 - 17:04:55) 334 main (Jul 25 2024 - 17:04:55) 1 Board_flashRead in SBL_ReadSysfwImage TIFS ver: 8.5.2--v08.05.02 (Chill Capybar SCISERVER Board Configuration header population... PASSED Sciclient_setBoardConfigHeader... PASSED 366 main (Jul 25 2024 - 17:04:55) 378 main (Jul 25 2024 - 17:04:55) Initlialzing PLLs ...done. InitlialzingClocks ...done. Initlialzing DDR ...01234560Board_DDRProbe: PASS Board_DDRInitDrv: PASS --->>> LPDDR4 Initialization is in progress ... <<<--- Reg Value: 128 Frequency Change type 1 request from Controller Reg Value: 0 Reg Value: 128 Frequency Change type 0 request from Controller Reg Value: 0 Reg Value: 128 Frequency Change type 1 request from Controller Reg Value: 0 Reg Value: 128 Frequency Change type 2 request from Controller Reg Value: 0 Reg Value: 128 Frequency Change type 1 request from Controller Reg Value: 0 Reg Value: 128 Frequency Change type 2 request from Controller --->>> Frequency Change request handshake is completed... <<<---
When I try to comment out the function void SBL_SciClientInit(uint32_t devGroup)
#if !defined(SBL_SKIP_MCU_RESET) /* RTI seems to be turned on by ROM. Turning it off so that Power domain can transition */ Sciclient_pmSetModuleState(SBL_DEV_ID_RTI0, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER); Sciclient_pmSetModuleState(SBL_DEV_ID_RTI1, TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER); #endif
It will get stuck for a while
log show
SBL Revision: 01.00.10.01 (Aug 12 2024 - 16:07:55) 306 main (Aug 12 2024 - 16:07:55) 320 main (Aug 12 2024 - 16:07:55) 329 main (Aug 12 2024 - 16:07:55) 334 main (Aug 12 2024 - 16:07:55) 1 Board_flashRead in SBL_ReadSysfwImage TIFS ver: 9.2.4--v09.02.04 (Kool Koala) SCISERVER Board Configuration header population... PASSED Sciclient_setBoardConfigHeader... PASSED 366 main (Aug 12 2024 - 16:07:55) 378 main (Aug 12 2024 - 16:07:55) Initlialzing PLLs ...
Hi,
sbl boot stuck for a while at
For additional debugging, could you kindly share your SBL pdk_j721s2_09_02_00_30/packages/ti/boot/sbl file with us?
Regards,
Karthik
The entire directory is too large and our company prohibits it, but I can take some code snippets for you to see.
Hi,
I can take some code snippets for you to see.
Yes, please share all of your modified code snippets.
Regards,
Karthik
---
.../ti/board/src/j721s2_evm/J721S2_pinmux.h | 448 ++--
.../board/src/j721s2_evm/J721S2_pinmux_data.c | 2228 +++++++++--------
.../src/j721s2_evm/include/board_ddrRegInit.h | 291 +--
.../src/j721s2_evm/include/board_internal.h | 4 +-
packages/ti/boot/sbl/board/k3/sbl_main.c | 4 +
packages/ti/boot/sbl/sbl_component.mk | 12 +-
packages/ti/boot/sbl/src/ospi/sbl_ospi.c | 2 +-
7 files changed, 1512 insertions(+), 1477 deletions(-)
mode change 100644 => 100755 packages/ti/board/src/j721s2_evm/J721S2_pinmux.h
mode change 100644 => 100755 packages/ti/board/src/j721s2_evm/J721S2_pinmux_data.c
mode change 100644 => 100755 packages/ti/board/src/j721s2_evm/include/board_ddrRegInit.h
mode change 100644 => 100755 packages/ti/board/src/j721s2_evm/include/board_internal.h
mode change 100644 => 100755 packages/ti/boot/sbl/sbl_component.mk
diff --git a/packages/ti/board/src/j721s2_evm/J721S2_pinmux.h b/packages/ti/board/src/j721s2_evm/J721S2_pinmux.h
old mode 100644
new mode 100755
index 4c09a581..8def4ee9
--- a/packages/ti/board/src/j721s2_evm/J721S2_pinmux.h
+++ b/packages/ti/board/src/j721s2_evm/J721S2_pinmux.h
@@ -1,220 +1,228 @@
-/**
- * Note: This file was auto-generated by TI PinMux on 10/24/2021.
- *
- * \file J721S2_pinmux.h
- *
- * \brief This file contains pad configure register offsets and bit-field
- * value macros for different configurations,
- *
- * BIT[21] TXDISABLE disable the pin's output driver
- * BIT[18] RXACTIVE enable the pin's input buffer (typically kept enabled)
- * BIT[17] PULLTYPESEL set the iternal resistor pull direction high or low (if enabled)
- * BIT[16] PULLUDEN internal resistor disable (0 = enabled / 1 = disabled)
- * BIT[3:0] MUXMODE select the desired function on the given pin
- *
- * \copyright Copyright (CU) 2021 Texas Instruments Incorporated -
- * http://www.ti.com/
- */
-
-#ifndef _J721S2_PIN_MUX_H_
-#define _J721S2_PIN_MUX_H_
-
-/* ========================================================================== */
-/* Include Files */
-/* ========================================================================== */
-
-#include "ti/board/src/j721s2_evm/include/pinmux.h"
-#include "ti/csl/csl_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* ========================================================================== */
-/* Macros & Typedefs */
-/* ========================================================================== */
-#define PIN_MODE(mode) (mode)
-#define PINMUX_END (-1)
-
-/** \brief Active mode configurations */
-/** \brief Resistor enable */
-#define PIN_PULL_DISABLE (0x1U << 16U)
-/** \brief Pull direction */
-#define PIN_PULL_DIRECTION (0x1U << 17U)
-/** \brief Receiver enable */
-#define PIN_INPUT_ENABLE (0x1U << 18U)
-/** \brief Driver disable */
-#define PIN_OUTPUT_DISABLE (0x1U << 21U)
-/** \brief Wakeup enable */
-#define PIN_WAKEUP_ENABLE (0x1U << 29U)
-
-/** \brief Pad config register offset in control module */
-
-enum pinMainOffsets
-{
- PIN_MCASP1_AXR0 = 0x0C0,
- PIN_MCASP1_AFSX = 0x0BC,
- PIN_MCASP1_ACLKX = 0x0B8,
- PIN_MCASP0_AXR12 = 0x0A0,
- PIN_MCASP0_AXR13 = 0x0A4,
- PIN_MCASP0_AXR14 = 0x0A8,
- PIN_MCASP1_AXR3 = 0x0B0,
- PIN_MCASP0_AXR15 = 0x0AC,
- PIN_MCASP0_AXR7 = 0x08C,
- PIN_MCASP0_AXR8 = 0x090,
- PIN_MCASP0_AXR9 = 0x094,
- PIN_MCASP0_AXR10 = 0x098,
- PIN_MCASP1_AXR4 = 0x0B4,
- PIN_MCASP0_AXR11 = 0x09C,
- PIN_MCAN13_TX = 0x00C,
- PIN_MCAN15_RX = 0x020,
- PIN_GPIO0_11 = 0x02C,
- PIN_PMIC_WAKE0 = 0x034,
- PIN_MCASP0_AXR2 = 0x048,
- PIN_MCASP2_AXR0 = 0x05C,
- PIN_MCAN0_RX = 0x068,
- PIN_MCAN1_RX = 0x070,
- PIN_SPI0_CS0 = 0x0CC,
- PIN_I2C0_SCL = 0x0E0,
- PIN_I2C0_SDA = 0x0E4,
- PIN_ECAP0_IN_APWM_OUT = 0x0C4,
- PIN_EXT_REFCLK1 = 0x0C8,
- PIN_MCAN0_TX = 0x064,
- PIN_MCASP2_AXR1 = 0x060,
- PIN_MCAN14_TX = 0x014,
- PIN_MCAN13_RX = 0x010,
- PIN_MCAN15_TX = 0x01C,
- PIN_MCAN14_RX = 0x018,
- PIN_MCAN16_RX = 0x028,
- PIN_MCAN16_TX = 0x024,
- PIN_MCASP0_AXR4 = 0x080,
- PIN_MCASP0_AXR3 = 0x07C,
- PIN_MCASP0_AFSX = 0x03C,
- PIN_MCASP0_ACLKX = 0x038,
- PIN_MCASP0_AXR6 = 0x088,
- PIN_MCASP0_AXR5 = 0x084,
- PIN_MMC1_CLK = 0x104,
- PIN_MMC1_CMD = 0x108,
- PIN_MMC1_CLKLB = 0x100,
- PIN_MMC1_DAT0 = 0x0FC,
- PIN_MMC1_DAT1 = 0x0F8,
- PIN_MMC1_DAT2 = 0x0F4,
- PIN_MMC1_DAT3 = 0x0F0,
- PIN_TIMER_IO0 = 0x0E8,
- PIN_EXTINTN = 0x000,
- PIN_RESETSTATZ = 0x10C,
- PIN_SOC_SAFETY_ERRORN = 0x110,
- PIN_MCASP0_AXR0 = 0x040,
- PIN_MCASP0_AXR1 = 0x044,
- PIN_SPI0_CS1 = 0x0D0,
- PIN_SPI0_CLK = 0x0D4,
- PIN_SPI0_D0 = 0x0D8,
- PIN_SPI0_D1 = 0x0DC,
- PIN_MCAN12_RX = 0x008,
- PIN_MCAN12_TX = 0x004,
- PIN_MCAN2_TX = 0x074,
- PIN_MCAN2_RX = 0x078,
- PIN_GPIO0_12 = 0x030,
- PIN_MCAN1_TX = 0x06C,
- PIN_MCASP1_AXR1 = 0x04C,
- PIN_MCASP1_AXR2 = 0x050,
- PIN_TIMER_IO1 = 0x0EC,
-};
-
-enum pinWkupOffsets
-{
- PIN_MCU_ADC0_AIN0 = 0x134,
- PIN_MCU_ADC0_AIN1 = 0x138,
- PIN_MCU_ADC0_AIN2 = 0x13C,
- PIN_MCU_ADC0_AIN3 = 0x140,
- PIN_MCU_ADC0_AIN4 = 0x144,
- PIN_MCU_ADC0_AIN5 = 0x148,
- PIN_MCU_ADC0_AIN6 = 0x14C,
- PIN_MCU_ADC0_AIN7 = 0x150,
- PIN_MCU_ADC1_AIN0 = 0x154,
- PIN_MCU_ADC1_AIN1 = 0x158,
- PIN_MCU_ADC1_AIN2 = 0x15C,
- PIN_MCU_ADC1_AIN3 = 0x160,
- PIN_MCU_ADC1_AIN4 = 0x164,
- PIN_MCU_ADC1_AIN5 = 0x168,
- PIN_MCU_ADC1_AIN6 = 0x16C,
- PIN_MCU_ADC1_AIN7 = 0x170,
- PIN_MCU_RGMII1_RD0 = 0x094,
- PIN_MCU_RGMII1_RD1 = 0x090,
- PIN_MCU_RGMII1_RD2 = 0x08C,
- PIN_MCU_RGMII1_RD3 = 0x088,
- PIN_MCU_RGMII1_RXC = 0x084,
- PIN_MCU_RGMII1_RX_CTL = 0x06C,
- PIN_MCU_RGMII1_TD0 = 0x07C,
- PIN_MCU_RGMII1_TD1 = 0x078,
- PIN_MCU_RGMII1_TD2 = 0x074,
- PIN_MCU_RGMII1_TD3 = 0x070,
- PIN_MCU_RGMII1_TXC = 0x080,
- PIN_MCU_RGMII1_TX_CTL = 0x068,
- PIN_MCU_I2C0_SCL = 0x108,
- PIN_MCU_I2C0_SDA = 0x10C,
- PIN_WKUP_GPIO0_8 = 0x0E0,
- PIN_WKUP_GPIO0_9 = 0x0E4,
- PIN_WKUP_GPIO0_11 = 0x0EC,
- PIN_MCU_MCAN0_RX = 0x0BC,
- PIN_MCU_MCAN0_TX = 0x0B8,
- PIN_WKUP_GPIO0_5 = 0x0D4,
- PIN_WKUP_GPIO0_4 = 0x0D0,
- PIN_MCU_MDIO0_MDC = 0x09C,
- PIN_MCU_MDIO0_MDIO = 0x098,
- PIN_MCU_OSPI0_CLK = 0x000,
- PIN_MCU_OSPI0_CSN0 = 0x02C,
- PIN_MCU_OSPI0_D0 = 0x00C,
- PIN_MCU_OSPI0_D1 = 0x010,
- PIN_MCU_OSPI0_D2 = 0x014,
- PIN_MCU_OSPI0_D3 = 0x018,
- PIN_MCU_OSPI0_D4 = 0x01C,
- PIN_MCU_OSPI0_D5 = 0x020,
- PIN_MCU_OSPI0_D6 = 0x024,
- PIN_MCU_OSPI0_D7 = 0x028,
- PIN_MCU_OSPI0_DQS = 0x008,
- PIN_MCU_OSPI0_CSN3 = 0x03C,
- PIN_MCU_OSPI0_CSN2 = 0x038,
- PIN_MCU_OSPI1_CLK = 0x040,
- PIN_MCU_OSPI1_CSN0 = 0x05C,
- PIN_MCU_OSPI1_D0 = 0x04C,
- PIN_MCU_OSPI1_D1 = 0x050,
- PIN_MCU_OSPI1_D2 = 0x054,
- PIN_MCU_OSPI1_D3 = 0x058,
- PIN_MCU_OSPI1_DQS = 0x048,
- PIN_MCU_OSPI1_LBCLKO = 0x044,
- PIN_WKUP_GPIO0_14 = 0x0F8,
- PIN_WKUP_GPIO0_15 = 0x0FC,
- PIN_WKUP_GPIO0_13 = 0x0F4,
- PIN_WKUP_GPIO0_12 = 0x0F0,
- PIN_WKUP_GPIO0_0 = 0x0C0,
- PIN_WKUP_GPIO0_1 = 0x0C4,
- PIN_WKUP_GPIO0_2 = 0x0C8,
- PIN_WKUP_GPIO0_3 = 0x0CC,
- PIN_WKUP_GPIO0_6 = 0x0D8,
- PIN_WKUP_GPIO0_7 = 0x0DC,
- PIN_MCU_OSPI1_CSN1 = 0x060,
- PIN_WKUP_GPIO0_49 = 0x190,
- PIN_MCU_SPI0_D0 = 0x0A4,
- PIN_WKUP_GPIO0_56 = 0x120,
- PIN_MCU_SPI0_D1 = 0x0A8,
- PIN_MCU_SPI0_CS0 = 0x0AC,
- PIN_WKUP_I2C0_SCL = 0x100,
- PIN_WKUP_I2C0_SDA = 0x104,
- PIN_WKUP_UART0_RXD = 0x0B0,
- PIN_WKUP_UART0_TXD = 0x0B4,
-};
-
-/* ========================================================================== */
-/* Global Variables */
-/* ========================================================================== */
-
-/** \brief Pinmux configuration data for the board. Auto-generated from
- Pinmux tool. */
-extern pinmuxBoardCfg_t gJ721S2_MainPinmuxData[];
-extern pinmuxBoardCfg_t gJ721S2_WkupPinmuxData[];
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-#endif /* _J721S2_PIN_MUX_H_ */
+/**
+ * Note: This file was auto-generated by TI PinMux on 5/8/2024.
+ *
+ * \file J721S2_pinmux.h
+ *
+ * \brief This file contains pad configure register offsets and bit-field
+ * value macros for different configurations,
+ *
+ * BIT[21] TXDISABLE disable the pin's output driver
+ * BIT[18] RXACTIVE enable the pin's input buffer (typically kept enabled)
+ * BIT[17] PULLTYPESEL set the iternal resistor pull direction high or low (if enabled)
+ * BIT[16] PULLUDEN internal resistor disable (0 = enabled / 1 = disabled)
+ * BIT[3:0] MUXMODE select the desired function on the given pin
+ *
+ * \copyright Copyright (CU) 2024 Texas Instruments Incorporated -
+ * http://www.ti.com/
+ */
+
+#ifndef _J721S2_PIN_MUX_H_
+#define _J721S2_PIN_MUX_H_
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include "include/pinmux.h"
+#include "ti/csl/csl_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+#define PIN_MODE(mode) (mode)
+#define PINMUX_END (-1)
+
+/** \brief Active mode configurations */
+/** \brief Resistor enable */
+#define PIN_PULL_DISABLE (0x1U << 16U)
+/** \brief Pull direction */
+#define PIN_PULL_DIRECTION (0x1U << 17U)
+/** \brief Receiver enable */
+#define PIN_INPUT_ENABLE (0x1U << 18U)
+/** \brief Driver disable */
+#define PIN_OUTPUT_DISABLE (0x1U << 21U)
+/** \brief Wakeup enable */
+#define PIN_WAKEUP_ENABLE (0x1U << 29U)
+
+/** \brief Pad config register offset in control module */
+
+enum pinMainOffsets
+{
+ PIN_MCASP1_AXR0 = 0x0C0,
+ PIN_MCASP1_AFSX = 0x0BC,
+ PIN_MCASP1_ACLKX = 0x0B8,
+ PIN_MCASP0_AXR12 = 0x0A0,
+ PIN_MCASP0_AXR13 = 0x0A4,
+ PIN_MCASP0_AXR14 = 0x0A8,
+ PIN_MCASP1_AXR3 = 0x0B0,
+ PIN_MCASP0_AXR15 = 0x0AC,
+ PIN_MCASP0_AXR7 = 0x08C,
+ PIN_MCASP0_AXR8 = 0x090,
+ PIN_MCASP0_AXR9 = 0x094,
+ PIN_MCASP0_AXR10 = 0x098,
+ PIN_MCASP1_AXR4 = 0x0B4,
+ PIN_MCASP0_AXR11 = 0x09C,
+ PIN_EXTINTN = 0x000,
+ PIN_GPIO0_11 = 0x02C,
+ PIN_GPIO0_12 = 0x030,
+ PIN_PMIC_WAKE0N = 0x034,
+ PIN_MCASP0_ACLKX = 0x038,
+ PIN_MCASP0_AFSX = 0x03C,
+ PIN_MCASP0_AXR0 = 0x040,
+ PIN_MCASP0_AXR1 = 0x044,
+ PIN_MCASP0_AXR2 = 0x048,
+ PIN_MCASP2_AXR0 = 0x05C,
+ PIN_MCASP2_AXR1 = 0x060,
+ PIN_MCAN1_TX = 0x06C,
+ PIN_MCAN1_RX = 0x070,
+ PIN_MCAN2_TX = 0x074,
+ PIN_MCAN2_RX = 0x078,
+ PIN_MCASP0_AXR3 = 0x07C,
+ PIN_MCASP0_AXR4 = 0x080,
+ PIN_MCASP0_AXR5 = 0x084,
+ PIN_MCASP0_AXR6 = 0x088,
+ PIN_SPI0_CS1 = 0x0D0,
+ PIN_TIMER_IO0 = 0x0E8,
+ PIN_MMC1_DAT3 = 0x0F0,
+ PIN_MMC1_DAT2 = 0x0F4,
+ PIN_I2C0_SCL = 0x0E0,
+ PIN_I2C0_SDA = 0x0E4,
+ PIN_MCASP1_AXR1 = 0x04C,
+ PIN_MCASP1_AXR2 = 0x050,
+ PIN_MMC1_DAT0 = 0x0FC,
+ PIN_MMC1_DAT1 = 0x0F8,
+ PIN_MMC1_CMD = 0x108,
+ PIN_MMC1_CLK = 0x104,
+ PIN_MCAN12_RX = 0x008,
+ PIN_MCAN12_TX = 0x004,
+ PIN_MCAN13_RX = 0x010,
+ PIN_MCAN13_TX = 0x00C,
+ PIN_MCAN14_RX = 0x018,
+ PIN_MCAN14_TX = 0x014,
+ PIN_MCAN15_RX = 0x020,
+ PIN_MCAN15_TX = 0x01C,
+ PIN_MCAN16_RX = 0x028,
+ PIN_MCAN16_TX = 0x024,
+ PIN_SPI0_CLK = 0x0D4,
+ PIN_SPI0_CS0 = 0x0CC,
+ PIN_SPI0_D0 = 0x0D8,
+ PIN_SPI0_D1 = 0x0DC,
+ PIN_TIMER_IO1 = 0x0EC,
+ PIN_ECAP0_IN_APWM_OUT = 0x0C4,
+ PIN_EXT_REFCLK1 = 0x0C8,
+ PIN_MCAN0_TX = 0x064,
+ PIN_MCAN0_RX = 0x068,
+ PIN_MCASP2_ACLKX = 0x054,
+ PIN_MCASP2_AFSX = 0x058,
+};
+
+enum pinWkupOffsets
+{
+ PIN_MCU_ADC0_AIN0 = 0x134,
+ PIN_MCU_ADC0_AIN1 = 0x138,
+ PIN_MCU_ADC0_AIN2 = 0x13C,
+ PIN_MCU_ADC0_AIN3 = 0x140,
+ PIN_MCU_ADC0_AIN4 = 0x144,
+ PIN_MCU_ADC0_AIN5 = 0x148,
+ PIN_MCU_ADC0_AIN6 = 0x14C,
+ PIN_MCU_ADC0_AIN7 = 0x150,
+ PIN_MCU_ADC1_AIN0 = 0x154,
+ PIN_MCU_ADC1_AIN1 = 0x158,
+ PIN_MCU_ADC1_AIN2 = 0x15C,
+ PIN_MCU_ADC1_AIN3 = 0x160,
+ PIN_MCU_ADC1_AIN4 = 0x164,
+ PIN_MCU_ADC1_AIN5 = 0x168,
+ PIN_MCU_ADC1_AIN6 = 0x16C,
+ PIN_MCU_ADC1_AIN7 = 0x170,
+ PIN_MCU_RGMII1_RD0 = 0x094,
+ PIN_MCU_RGMII1_RD1 = 0x090,
+ PIN_MCU_RGMII1_RD2 = 0x08C,
+ PIN_MCU_RGMII1_RD3 = 0x088,
+ PIN_MCU_RGMII1_RXC = 0x084,
+ PIN_MCU_RGMII1_RX_CTL = 0x06C,
+ PIN_MCU_RGMII1_TD0 = 0x07C,
+ PIN_MCU_RGMII1_TD1 = 0x078,
+ PIN_MCU_RGMII1_TD2 = 0x074,
+ PIN_MCU_RGMII1_TD3 = 0x070,
+ PIN_MCU_RGMII1_TXC = 0x080,
+ PIN_MCU_RGMII1_TX_CTL = 0x068,
+ PIN_MCU_I2C0_SCL = 0x108,
+ PIN_MCU_I2C0_SDA = 0x10C,
+ PIN_WKUP_GPIO0_6 = 0x0D8,
+ PIN_WKUP_GPIO0_7 = 0x0DC,
+ PIN_MCU_MCAN0_RX = 0x0BC,
+ PIN_MCU_MCAN0_TX = 0x0B8,
+ PIN_WKUP_GPIO0_5 = 0x0D4,
+ PIN_WKUP_GPIO0_4 = 0x0D0,
+ PIN_MCU_MDIO0_MDC = 0x09C,
+ PIN_MCU_MDIO0_MDIO = 0x098,
+ PIN_MCU_OSPI0_CLK = 0x000,
+ PIN_MCU_OSPI0_CSN0 = 0x02C,
+ PIN_MCU_OSPI0_D0 = 0x00C,
+ PIN_MCU_OSPI0_D1 = 0x010,
+ PIN_MCU_OSPI0_D2 = 0x014,
+ PIN_MCU_OSPI0_D3 = 0x018,
+ PIN_MCU_OSPI0_D4 = 0x01C,
+ PIN_MCU_OSPI0_D5 = 0x020,
+ PIN_MCU_OSPI0_D6 = 0x024,
+ PIN_MCU_OSPI0_D7 = 0x028,
+ PIN_MCU_OSPI0_DQS = 0x008,
+ PIN_MCU_OSPI0_CSN2 = 0x038,
+ PIN_MCU_SPI0_CLK = 0x0A0,
+ PIN_MCU_SPI0_D0 = 0x0A4,
+ PIN_MCU_SPI0_D1 = 0x0A8,
+ PIN_WKUP_GPIO0_13 = 0x0F4,
+ PIN_WKUP_GPIO0_12 = 0x0F0,
+ PIN_WKUP_GPIO0_0 = 0x0C0,
+ PIN_WKUP_GPIO0_1 = 0x0C4,
+ PIN_WKUP_GPIO0_2 = 0x0C8,
+ PIN_WKUP_GPIO0_3 = 0x0CC,
+ PIN_WKUP_GPIO0_8 = 0x0E0,
+ PIN_WKUP_GPIO0_9 = 0x0E4,
+ PIN_WKUP_GPIO0_10 = 0x0E8,
+ PIN_WKUP_GPIO0_11 = 0x0EC,
+ PIN_WKUP_GPIO0_14 = 0x0F8,
+ PIN_WKUP_GPIO0_15 = 0x0FC,
+ PIN_MCU_OSPI0_LBCLKO = 0x004,
+ PIN_MCU_OSPI0_CSN1 = 0x030,
+ PIN_MCU_OSPI0_CSN3 = 0x03C,
+ PIN_MCU_OSPI1_CLK = 0x040,
+ PIN_MCU_OSPI1_LBCLKO = 0x044,
+ PIN_MCU_OSPI1_DQS = 0x048,
+ PIN_MCU_OSPI1_D0 = 0x04C,
+ PIN_MCU_OSPI1_D1 = 0x050,
+ PIN_MCU_OSPI1_D2 = 0x054,
+ PIN_MCU_OSPI1_D3 = 0x058,
+ PIN_MCU_OSPI1_CSN0 = 0x05C,
+ PIN_MCU_OSPI1_CSN1 = 0x060,
+ PIN_WKUP_GPIO0_49 = 0x190,
+ PIN_WKUP_GPIO0_56 = 0x120,
+ PIN_WKUP_GPIO0_57 = 0x17C,
+ PIN_WKUP_GPIO0_66 = 0x180,
+ PIN_WKUP_GPIO0_67 = 0x184,
+ PIN_MCU_SPI0_CS0 = 0x0AC,
+ PIN_PMIC_POWER_EN1 = 0x110,
+ PIN_WKUP_I2C0_SCL = 0x100,
+ PIN_WKUP_I2C0_SDA = 0x104,
+ PIN_MCU_RESETSTATZ = 0x11C,
+ PIN_WKUP_UART0_RXD = 0x0B0,
+ PIN_WKUP_UART0_TXD = 0x0B4,
+};
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+/** \brief Pinmux configuration data for the board. Auto-generated from
+ Pinmux tool. */
+extern pinmuxBoardCfg_t gJ721S2_MainPinmuxData[];
+extern pinmuxBoardCfg_t gJ721S2_WkupPinmuxData[];
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _J721S2_PIN_MUX_H_ */
diff --git a/packages/ti/board/src/j721s2_evm/J721S2_pinmux_data.c b/packages/ti/board/src/j721s2_evm/J721S2_pinmux_data.c
old mode 100644
new mode 100755
index 2f8c7413..db917d5b
--- a/packages/ti/board/src/j721s2_evm/J721S2_pinmux_data.c
+++ b/packages/ti/board/src/j721s2_evm/J721S2_pinmux_data.c
@@ -1,1103 +1,1125 @@
-/**
-* Note: This file was auto-generated by TI PinMux on 10/24/2021 at 3:31:41 AM.
-*
-* \file J721S2_pinmux_data.c
-*
-* \brief This file contains the pin mux configurations for the boards.
-* These are prepared based on how the peripherals are extended on
-* the boards.
-*
-* \copyright Copyright (CU) 2021 Texas Instruments Incorporated -
-* http://www.ti.com/
-*/
-
-/* ========================================================================== */
-/* Include Files */
-/* ========================================================================== */
-
-#include "J721S2_pinmux.h"
-
-/** Peripheral Pin Configurations */
-
-
-static pinmuxPerCfg_t gCpsw2g0PinCfg[] =
-{
- /* MyCPSW2G0 -> MDIO0_MDC -> T28 */
- {
- PIN_MCASP1_AXR0, PIN_MODE(6) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyCPSW2G0 -> MDIO0_MDIO -> V28 */
- {
- PIN_MCASP1_AFSX, PIN_MODE(6) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyCPSW2G0 -> RGMII1_RD0 -> AA24 */
- {
- PIN_MCASP1_ACLKX, PIN_MODE(6) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyCPSW2G0 -> RGMII1_RD1 -> AB25 */
- {
- PIN_MCASP0_AXR12, PIN_MODE(6) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyCPSW2G0 -> RGMII1_RD2 -> T23 */
- {
- PIN_MCASP0_AXR13, PIN_MODE(6) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyCPSW2G0 -> RGMII1_RD3 -> U24 */
- {
- PIN_MCASP0_AXR14, PIN_MODE(6) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyCPSW2G0 -> RGMII1_RXC -> AD26 */
- {
- PIN_MCASP1_AXR3, PIN_MODE(6) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyCPSW2G0 -> RGMII1_RX_CTL -> AC25 */
- {
- PIN_MCASP0_AXR15, PIN_MODE(6) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyCPSW2G0 -> RGMII1_TD0 -> T25 */
- {
- PIN_MCASP0_AXR7, PIN_MODE(6) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyCPSW2G0 -> RGMII1_TD1 -> W24 */
- {
- PIN_MCASP0_AXR8, PIN_MODE(6) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyCPSW2G0 -> RGMII1_TD2 -> AA25 */
- {
- PIN_MCASP0_AXR9, PIN_MODE(6) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyCPSW2G0 -> RGMII1_TD3 -> V25 */
- {
- PIN_MCASP0_AXR10, PIN_MODE(6) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyCPSW2G0 -> RGMII1_TXC -> U25 */
- {
- PIN_MCASP1_AXR4, PIN_MODE(6) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyCPSW2G0 -> RGMII1_TX_CTL -> T24 */
- {
- PIN_MCASP0_AXR11, PIN_MODE(6) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxModuleCfg_t gCpsw2gPinCfg[] =
-{
- {0, 1, gCpsw2g0PinCfg},
- {PINMUX_END}
-};
-
-
-static pinmuxPerCfg_t gGpio0PinCfg[] =
-{
- /* MyGPIO0 -> GPIO0_3 -> AE28 */
- {
- PIN_MCAN13_TX, PIN_MODE(7) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyGPIO0 -> GPIO0_8 -> AA23 */
- {
- PIN_MCAN15_RX, PIN_MODE(7) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyGPIO0 -> GPIO0_11 -> V23 */
- {
- PIN_GPIO0_11, PIN_MODE(7) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyGPIO0 -> GPIO0_13 -> AD24 */
- {
- PIN_PMIC_WAKE0, PIN_MODE(7) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyGPIO0 -> GPIO0_18 -> AB27 */
- {
- PIN_MCASP0_AXR2, PIN_MODE(7) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyGPIO0 -> GPIO0_23 -> AA26 */
- {
- PIN_MCASP2_AXR0, PIN_MODE(7) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyGPIO0 -> GPIO0_26 -> U28 */
- {
- PIN_MCAN0_RX, PIN_MODE(7) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyGPIO0 -> GPIO0_28 -> R27 */
- {
- PIN_MCAN1_RX, PIN_MODE(7) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyGPIO0 -> GPIO0_51 -> AE27 */
- {
- PIN_SPI0_CS0, PIN_MODE(7) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxModuleCfg_t gGpioPinCfg[] =
-{
- {0, 1, gGpio0PinCfg},
- {PINMUX_END}
-};
-
-
-static pinmuxPerCfg_t gI2c0PinCfg[] =
-{
- /* MyI2C0 -> I2C0_SCL -> AH25 */
- {
- PIN_I2C0_SCL, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyI2C0 -> I2C0_SDA -> AE24 */
- {
- PIN_I2C0_SDA, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxPerCfg_t gI2c1PinCfg[] =
-{
- /* MyI2C1 -> I2C1_SCL -> AB26 */
- {
- PIN_ECAP0_IN_APWM_OUT, PIN_MODE(13) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyI2C1 -> I2C1_SDA -> AD28 */
- {
- PIN_EXT_REFCLK1, PIN_MODE(13) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxPerCfg_t gI2c3PinCfg[] =
-{
- /* MyI2C3 -> I2C3_SCL -> W28 */
- {
- PIN_MCAN0_TX, PIN_MODE(13) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyI2C3 -> I2C3_SDA -> AC27 */
- {
- PIN_MCASP2_AXR1, PIN_MODE(13) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxPerCfg_t gI2c4PinCfg[] =
-{
- /* MyI2C4 -> I2C4_SCL -> AD25 */
- {
- PIN_MCAN14_TX, PIN_MODE(8) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyI2C4 -> I2C4_SDA -> AF28 */
- {
- PIN_MCAN13_RX, PIN_MODE(8) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxPerCfg_t gI2c5PinCfg[] =
-{
- /* MyI2C5 -> I2C5_SCL -> Y24 */
- {
- PIN_MCAN15_TX, PIN_MODE(8) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyI2C5 -> I2C5_SDA -> W23 */
- {
- PIN_MCAN14_RX, PIN_MODE(8) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxModuleCfg_t gI2cPinCfg[] =
-{
- {0, 1, gI2c0PinCfg},
- {1, 1, gI2c1PinCfg},
- {3, 1, gI2c3PinCfg},
- {4, 1, gI2c4PinCfg},
- {5, 1, gI2c5PinCfg},
- {PINMUX_END}
-};
-
-
-static pinmuxPerCfg_t gMcan6PinCfg[] =
-{
- /* MyMCAN16 -> MCAN16_RX -> AB24 */
- {
- PIN_MCAN16_RX, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCAN16 -> MCAN16_TX -> Y28 */
- {
- PIN_MCAN16_TX, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxPerCfg_t gMcan3PinCfg[] =
-{
- /* MyMCAN3 -> MCAN3_RX -> U26 */
- {
- PIN_MCASP0_AXR4, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCAN3 -> MCAN3_TX -> T27 */
- {
- PIN_MCASP0_AXR3, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxPerCfg_t gMcan5PinCfg[] =
-{
- /* MyMCAN5 -> MCAN5_RX -> U27 */
- {
- PIN_MCASP0_AFSX, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCAN5 -> MCAN5_TX -> AB28 */
- {
- PIN_MCASP0_ACLKX, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxPerCfg_t gMcan4PinCfg[] =
-{
- /* MyMCAN4 -> MCAN4_RX -> AD27 */
- {
- PIN_MCASP0_AXR6, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCAN4 -> MCAN4_TX -> AA28 */
- {
- PIN_MCASP0_AXR5, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxModuleCfg_t gMcanPinCfg[] =
-{
- {6, 1, gMcan6PinCfg},
- {3, 1, gMcan3PinCfg},
- {5, 1, gMcan5PinCfg},
- {4, 1, gMcan4PinCfg},
- {PINMUX_END}
-};
-
-
-static pinmuxPerCfg_t gMcu_adc0PinCfg[] =
-{
- /* MyMCU_ADC0 -> MCU_ADC0_AIN0 -> L25 */
- {
- PIN_MCU_ADC0_AIN0, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_ADC0 -> MCU_ADC0_AIN1 -> K25 */
- {
- PIN_MCU_ADC0_AIN1, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_ADC0 -> MCU_ADC0_AIN2 -> M24 */
- {
- PIN_MCU_ADC0_AIN2, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_ADC0 -> MCU_ADC0_AIN3 -> L24 */
- {
- PIN_MCU_ADC0_AIN3, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_ADC0 -> MCU_ADC0_AIN4 -> L27 */
- {
- PIN_MCU_ADC0_AIN4, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_ADC0 -> MCU_ADC0_AIN5 -> K24 */
- {
- PIN_MCU_ADC0_AIN5, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_ADC0 -> MCU_ADC0_AIN6 -> M27 */
- {
- PIN_MCU_ADC0_AIN6, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_ADC0 -> MCU_ADC0_AIN7 -> M26 */
- {
- PIN_MCU_ADC0_AIN7, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxPerCfg_t gMcu_adc1PinCfg[] =
-{
- /* MyMCU_ADC1 -> MCU_ADC1_AIN0 -> P25 */
- {
- PIN_MCU_ADC1_AIN0, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_ADC1 -> MCU_ADC1_AIN1 -> R25 */
- {
- PIN_MCU_ADC1_AIN1, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_ADC1 -> MCU_ADC1_AIN2 -> P28 */
- {
- PIN_MCU_ADC1_AIN2, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_ADC1 -> MCU_ADC1_AIN3 -> P27 */
- {
- PIN_MCU_ADC1_AIN3, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_ADC1 -> MCU_ADC1_AIN4 -> N25 */
- {
- PIN_MCU_ADC1_AIN4, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_ADC1 -> MCU_ADC1_AIN5 -> P26 */
- {
- PIN_MCU_ADC1_AIN5, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_ADC1 -> MCU_ADC1_AIN6 -> N26 */
- {
- PIN_MCU_ADC1_AIN6, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_ADC1 -> MCU_ADC1_AIN7 -> N27 */
- {
- PIN_MCU_ADC1_AIN7, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxModuleCfg_t gMcu_adcPinCfg[] =
-{
- {0, 1, gMcu_adc0PinCfg},
- {1, 1, gMcu_adc1PinCfg},
- {PINMUX_END}
-};
-
-
-static pinmuxPerCfg_t gMcu_cpsw2g0PinCfg[] =
-{
- /* MyMCU_CPSW2G0 -> MCU_RGMII1_RD0 -> B22 */
- {
- PIN_MCU_RGMII1_RD0, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_CPSW2G0 -> MCU_RGMII1_RD1 -> B21 */
- {
- PIN_MCU_RGMII1_RD1, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_CPSW2G0 -> MCU_RGMII1_RD2 -> C22 */
- {
- PIN_MCU_RGMII1_RD2, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_CPSW2G0 -> MCU_RGMII1_RD3 -> D23 */
- {
- PIN_MCU_RGMII1_RD3, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_CPSW2G0 -> MCU_RGMII1_RXC -> D22 */
- {
- PIN_MCU_RGMII1_RXC, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_CPSW2G0 -> MCU_RGMII1_RX_CTL -> E23 */
- {
- PIN_MCU_RGMII1_RX_CTL, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_CPSW2G0 -> MCU_RGMII1_TD0 -> F23 */
- {
- PIN_MCU_RGMII1_TD0, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_CPSW2G0 -> MCU_RGMII1_TD1 -> G22 */
- {
- PIN_MCU_RGMII1_TD1, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_CPSW2G0 -> MCU_RGMII1_TD2 -> E21 */
- {
- PIN_MCU_RGMII1_TD2, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_CPSW2G0 -> MCU_RGMII1_TD3 -> E22 */
- {
- PIN_MCU_RGMII1_TD3, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_CPSW2G0 -> MCU_RGMII1_TXC -> F21 */
- {
- PIN_MCU_RGMII1_TXC, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_CPSW2G0 -> MCU_RGMII1_TX_CTL -> F22 */
- {
- PIN_MCU_RGMII1_TX_CTL, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxModuleCfg_t gMcu_cpsw2gPinCfg[] =
-{
- {0, 1, gMcu_cpsw2g0PinCfg},
- {PINMUX_END}
-};
-
-
-static pinmuxPerCfg_t gMcu_i2c0PinCfg[] =
-{
- /* MyMCU_I2C0 -> MCU_I2C0_SCL -> G24 */
- {
- PIN_MCU_I2C0_SCL, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_I2C0 -> MCU_I2C0_SDA -> J25 */
- {
- PIN_MCU_I2C0_SDA, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxModuleCfg_t gMcu_i2cPinCfg[] =
-{
- {0, 1, gMcu_i2c0PinCfg},
- {PINMUX_END}
-};
-
-
-static pinmuxPerCfg_t gMcu_i3c0PinCfg[] =
-{
- /* MyMCU_I3C1 -> MCU_I3C0_SCL -> F24 */
- {
- PIN_WKUP_GPIO0_8, PIN_MODE(3) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_I3C1 -> MCU_I3C0_SDA -> H26 */
- {
- PIN_WKUP_GPIO0_9, PIN_MODE(3) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_I3C1 -> MCU_I3C0_SDAPULLEN -> F25 */
- {
- PIN_WKUP_GPIO0_11, PIN_MODE(5) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxModuleCfg_t gMcu_i3cPinCfg[] =
-{
- {0, 1, gMcu_i3c0PinCfg},
- {PINMUX_END}
-};
-
-
-static pinmuxPerCfg_t gMcu_mcan0PinCfg[] =
-{
- /* MyMCU_MCAN0 -> MCU_MCAN0_RX -> E28 */
- {
- PIN_MCU_MCAN0_RX, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_MCAN0 -> MCU_MCAN0_TX -> E27 */
- {
- PIN_MCU_MCAN0_TX, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxPerCfg_t gMcu_mcan1PinCfg[] =
-{
- /* MyMCU_MCAN1 -> MCU_MCAN1_RX -> F26 */
- {
- PIN_WKUP_GPIO0_5, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_MCAN1 -> MCU_MCAN1_TX -> C23 */
- {
- PIN_WKUP_GPIO0_4, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxModuleCfg_t gMcu_mcanPinCfg[] =
-{
- {0, 1, gMcu_mcan0PinCfg},
- {1, 1, gMcu_mcan1PinCfg},
- {PINMUX_END}
-};
-
-
-static pinmuxPerCfg_t gMcu_mdio0PinCfg[] =
-{
- /* MyMCU_MDIO0 -> MCU_MDIO0_MDC -> A21 */
- {
- PIN_MCU_MDIO0_MDC, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_MDIO0 -> MCU_MDIO0_MDIO -> A22 */
- {
- PIN_MCU_MDIO0_MDIO, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxModuleCfg_t gMcu_mdioPinCfg[] =
-{
- {0, 1, gMcu_mdio0PinCfg},
- {PINMUX_END}
-};
-
-
-static pinmuxPerCfg_t gMcu_ospi0PinCfg[] =
-{
- /* MyMCU_OSPI0 -> MCU_OSPI0_CLK -> D19 */
- {
- PIN_MCU_OSPI0_CLK, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_OSPI0 -> MCU_OSPI0_CSn0 -> F15 */
- {
- PIN_MCU_OSPI0_CSN0, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_OSPI0 -> MCU_OSPI0_D0 -> C19 */
- {
- PIN_MCU_OSPI0_D0, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_OSPI0 -> MCU_OSPI0_D1 -> F16 */
- {
- PIN_MCU_OSPI0_D1, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_OSPI0 -> MCU_OSPI0_D2 -> G15 */
- {
- PIN_MCU_OSPI0_D2, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_OSPI0 -> MCU_OSPI0_D3 -> F18 */
- {
- PIN_MCU_OSPI0_D3, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_OSPI0 -> MCU_OSPI0_D4 -> E19 */
- {
- PIN_MCU_OSPI0_D4, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_OSPI0 -> MCU_OSPI0_D5 -> G19 */
- {
- PIN_MCU_OSPI0_D5, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_OSPI0 -> MCU_OSPI0_D6 -> F19 */
- {
- PIN_MCU_OSPI0_D6, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_OSPI0 -> MCU_OSPI0_D7 -> F20 */
- {
- PIN_MCU_OSPI0_D7, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_OSPI0 -> MCU_OSPI0_DQS -> E18 */
- {
- PIN_MCU_OSPI0_DQS, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_OSPI0 -> MCU_OSPI0_ECC_FAIL -> F17 */
- {
- PIN_MCU_OSPI0_CSN3, PIN_MODE(6) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_OSPI0 -> MCU_OSPI0_RESET_OUT0 -> F14 */
- {
- PIN_MCU_OSPI0_CSN2, PIN_MODE(6) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxPerCfg_t gMcu_ospi1PinCfg[] =
-{
- /* MyMCU_OSPI1 -> MCU_OSPI1_CLK -> A19 */
- {
- PIN_MCU_OSPI1_CLK, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_OSPI1 -> MCU_OSPI1_CSn0 -> D20 */
- {
- PIN_MCU_OSPI1_CSN0, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_OSPI1 -> MCU_OSPI1_D0 -> D21 */
- {
- PIN_MCU_OSPI1_D0, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_OSPI1 -> MCU_OSPI1_D1 -> G20 */
- {
- PIN_MCU_OSPI1_D1, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_OSPI1 -> MCU_OSPI1_D2 -> C20 */
- {
- PIN_MCU_OSPI1_D2, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_OSPI1 -> MCU_OSPI1_D3 -> A20 */
- {
- PIN_MCU_OSPI1_D3, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_OSPI1 -> MCU_OSPI1_DQS -> B19 */
- {
- PIN_MCU_OSPI1_DQS, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_OSPI1 -> MCU_OSPI1_LBCLKO -> B20 */
- {
- PIN_MCU_OSPI1_LBCLKO, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxModuleCfg_t gMcu_ospiPinCfg[] =
-{
- {0, 1, gMcu_ospi0PinCfg},
- {1, 1, gMcu_ospi1PinCfg},
- {PINMUX_END}
-};
-
-
-static pinmuxPerCfg_t gMcu_uart0PinCfg[] =
-{
- /* MyMCU_UART0 -> MCU_UART0_CTSn -> B24 */
- {
- PIN_WKUP_GPIO0_14, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_UART0 -> MCU_UART0_RTSn -> D25 */
- {
- PIN_WKUP_GPIO0_15, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_UART0 -> MCU_UART0_RXD -> C24 */
- {
- PIN_WKUP_GPIO0_13, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMCU_UART0 -> MCU_UART0_TXD -> C25 */
- {
- PIN_WKUP_GPIO0_12, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxModuleCfg_t gMcu_uartPinCfg[] =
-{
- {0, 1, gMcu_uart0PinCfg},
- {PINMUX_END}
-};
-
-
-static pinmuxPerCfg_t gMmcsd1PinCfg[] =
-{
- /* MyMMCSD1 -> MMC1_CLK -> P23 */
- {
- PIN_MMC1_CLK, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMMCSD1 -> MMC1_CMD -> N24 */
- {
- PIN_MMC1_CMD, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMMCSD1 -> MMC1_DAT0 -> M23 */
- {
- PIN_MMC1_DAT0, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMMCSD1 -> MMC1_DAT1 -> P24 */
- {
- PIN_MMC1_DAT1, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMMCSD1 -> MMC1_DAT2 -> R24 */
- {
- PIN_MMC1_DAT2, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMMCSD1 -> MMC1_DAT3 -> R22 */
- {
- PIN_MMC1_DAT3, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMMCSD1 -> MMC1_SDCD -> AE25 */
- {
- PIN_TIMER_IO0, PIN_MODE(8) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyMMC1 -> MMC1_CLKLB */
- {
- PIN_MMC1_CLKLB, PIN_MODE(0) | \
- ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
- },
- {PINMUX_END}
-};
-
-static pinmuxModuleCfg_t gMmcsdPinCfg[] =
-{
- {1, 1, gMmcsd1PinCfg},
- {PINMUX_END}
-};
-
-
-static pinmuxPerCfg_t gSystem0PinCfg[] =
-{
- /* MySYSTEM0 -> EXTINTn -> AG24 */
- {
- PIN_EXTINTN, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MySYSTEM0 -> RESETSTATz -> AF27 */
- {
- PIN_RESETSTATZ, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MySYSTEM0 -> SOC_SAFETY_ERRORn -> AF25 */
- {
- PIN_SOC_SAFETY_ERRORN, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxModuleCfg_t gSystemPinCfg[] =
-{
- {0, 1, gSystem0PinCfg},
- {PINMUX_END}
-};
-
-
-static pinmuxPerCfg_t gUart8PinCfg[] =
-{
- /* MyUART8 -> UART8_CTSn -> AC28 */
- {
- PIN_MCASP0_AXR0, PIN_MODE(14) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyUART8 -> UART8_RTSn -> Y26 */
- {
- PIN_MCASP0_AXR1, PIN_MODE(14) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyUART8 -> UART8_RXD -> AF26 */
- {
- PIN_SPI0_CS1, PIN_MODE(11) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyUART8 -> UART8_TXD -> AH27 */
- {
- PIN_SPI0_CLK, PIN_MODE(11) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxPerCfg_t gUart2PinCfg[] =
-{
- /* MyUART2 -> UART2_RXD -> AG26 */
- {
- PIN_SPI0_D0, PIN_MODE(11) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyUART2 -> UART2_TXD -> AH26 */
- {
- PIN_SPI0_D1, PIN_MODE(11) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxPerCfg_t gUart5PinCfg[] =
-{
- /* MyUART5 -> UART5_RXD -> AC24 */
- {
- PIN_MCAN12_RX, PIN_MODE(11) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyUART5 -> UART5_TXD -> W25 */
- {
- PIN_MCAN12_TX, PIN_MODE(11) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxPerCfg_t gUart3PinCfg[] =
-{
- /* MyUART3 -> UART3_RXD -> R28 */
- {
- PIN_MCAN2_TX, PIN_MODE(11) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyUART3 -> UART3_TXD -> Y25 */
- {
- PIN_MCAN2_RX, PIN_MODE(11) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxPerCfg_t gUart6PinCfg[] =
-{
- /* MyUART6 -> UART6_RXD -> T26 */
- {
- PIN_GPIO0_12, PIN_MODE(12) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyUART6 -> UART6_TXD -> V26 */
- {
- PIN_MCAN1_TX, PIN_MODE(11) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxPerCfg_t gUart9PinCfg[] =
-{
- /* MyUART9 -> UART9_RXD -> V27 */
- {
- PIN_MCASP1_AXR1, PIN_MODE(12) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyUART9 -> UART9_TXD -> W27 */
- {
- PIN_MCASP1_AXR2, PIN_MODE(12) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxModuleCfg_t gUartPinCfg[] =
-{
- {8, 1, gUart8PinCfg},
- {2, 1, gUart2PinCfg},
- {5, 1, gUart5PinCfg},
- {3, 1, gUart3PinCfg},
- {6, 1, gUart6PinCfg},
- {9, 1, gUart9PinCfg},
- {PINMUX_END}
-};
-
-
-static pinmuxPerCfg_t gUsb0PinCfg[] =
-{
- /* MyUSB0 -> USB0_DRVVBUS -> AG25 */
- {
- PIN_TIMER_IO1, PIN_MODE(6) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxModuleCfg_t gUsbPinCfg[] =
-{
- {0, 1, gUsb0PinCfg},
- {PINMUX_END}
-};
-
-
-static pinmuxPerCfg_t gWkup_gpio0PinCfg[] =
-{
- /* MyWKUP_GPIO0 -> WKUP_GPIO0_0 -> D26 */
- {
- PIN_WKUP_GPIO0_0, PIN_MODE(7) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyWKUP_GPIO0 -> WKUP_GPIO0_1 -> E24 */
- {
- PIN_WKUP_GPIO0_1, PIN_MODE(7) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyWKUP_GPIO0 -> WKUP_GPIO0_2 -> C28 */
- {
- PIN_WKUP_GPIO0_2, PIN_MODE(7) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyWKUP_GPIO0 -> WKUP_GPIO0_3 -> C27 */
- {
- PIN_WKUP_GPIO0_3, PIN_MODE(7) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyWKUP_GPIO0 -> WKUP_GPIO0_6 -> E25 */
- {
- PIN_WKUP_GPIO0_6, PIN_MODE(7) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyWKUP_GPIO0 -> WKUP_GPIO0_7 -> F28 */
- {
- PIN_WKUP_GPIO0_7, PIN_MODE(7) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyWKUP_GPIO0 -> WKUP_GPIO0_39 -> C21 */
- {
- PIN_MCU_OSPI1_CSN1, PIN_MODE(7) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyWKUP_GPIO0 -> WKUP_GPIO0_49 -> K26 */
- {
- PIN_WKUP_GPIO0_49, PIN_MODE(7) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyWKUP_GPIO0 -> WKUP_GPIO0_55 -> D24 */
- {
- PIN_MCU_SPI0_D0, PIN_MODE(7) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyWKUP_GPIO0 -> WKUP_GPIO0_56 -> G27 */
- {
- PIN_WKUP_GPIO0_56, PIN_MODE(7) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyWKUP_GPIO0 -> WKUP_GPIO0_69 -> B25 */
- {
- PIN_MCU_SPI0_D1, PIN_MODE(7) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyWKUP_GPIO0 -> WKUP_GPIO0_70 -> B26 */
- {
- PIN_MCU_SPI0_CS0, PIN_MODE(7) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxModuleCfg_t gWkup_gpioPinCfg[] =
-{
- {0, 1, gWkup_gpio0PinCfg},
- {PINMUX_END}
-};
-
-
-static pinmuxPerCfg_t gWkup_i2c0PinCfg[] =
-{
- /* MyWKUP_I2C0 -> WKUP_I2C0_SCL -> H24 */
- {
- PIN_WKUP_I2C0_SCL, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyWKUP_I2C0 -> WKUP_I2C0_SDA -> H27 */
- {
- PIN_WKUP_I2C0_SDA, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxModuleCfg_t gWkup_i2cPinCfg[] =
-{
- {0, 1, gWkup_i2c0PinCfg},
- {PINMUX_END}
-};
-
-
-static pinmuxPerCfg_t gWkup_uart0PinCfg[] =
-{
- /* MyWKUP_UART0 -> WKUP_UART0_RXD -> D28 */
- {
- PIN_WKUP_UART0_RXD, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- /* MyWKUP_UART0 -> WKUP_UART0_TXD -> D27 */
- {
- PIN_WKUP_UART0_TXD, PIN_MODE(0) | \
- ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-
-static pinmuxModuleCfg_t gWkup_uartPinCfg[] =
-{
- {0, 1, gWkup_uart0PinCfg},
- {PINMUX_END}
-};
-
-
-pinmuxBoardCfg_t gJ721S2_MainPinmuxData[] =
-{
- {0, gCpsw2gPinCfg},
- {1, gGpioPinCfg},
- {2, gI2cPinCfg},
- {3, gMcanPinCfg},
- {4, gMmcsdPinCfg},
- {5, gSystemPinCfg},
- {6, gUartPinCfg},
- {7, gUsbPinCfg},
- {PINMUX_END}
-};
-
-pinmuxBoardCfg_t gJ721S2_WkupPinmuxData[] =
-{
- {0, gMcu_adcPinCfg},
- {1, gMcu_cpsw2gPinCfg},
- {2, gMcu_i2cPinCfg},
- {3, gMcu_i3cPinCfg},
- {4, gMcu_mcanPinCfg},
- {5, gMcu_mdioPinCfg},
- {6, gMcu_ospiPinCfg},
- {7, gMcu_uartPinCfg},
- {8, gWkup_gpioPinCfg},
- {9, gWkup_i2cPinCfg},
- {10, gWkup_uartPinCfg},
- {PINMUX_END}
-};
+/**
+* Note: This file was auto-generated by TI PinMux on 5/8/2024 at 11:10:26 AM.
+*
+* \file J721S2_pinmux_data.c
+*
+* \brief This file contains the pin mux configurations for the boards.
+* These are prepared based on how the peripherals are extended on
+* the boards.
+*
+* \copyright Copyright (CU) 2024 Texas Instruments Incorporated -
+* http://www.ti.com/
+*/
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include "J721S2_pinmux.h"
+
+/** Peripheral Pin Configurations */
+
+
+static pinmuxPerCfg_t gCpsw2g0PinCfg[] =
+{
+ /* main_CPSW2G0 -> MDIO0_MDC -> T28 */
+ {
+ PIN_MCASP1_AXR0, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_CPSW2G0 -> MDIO0_MDIO -> V28 */
+ {
+ PIN_MCASP1_AFSX, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_CPSW2G0 -> RGMII1_RD0 -> AA24 */
+ {
+ PIN_MCASP1_ACLKX, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_CPSW2G0 -> RGMII1_RD1 -> AB25 */
+ {
+ PIN_MCASP0_AXR12, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_CPSW2G0 -> RGMII1_RD2 -> T23 */
+ {
+ PIN_MCASP0_AXR13, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_CPSW2G0 -> RGMII1_RD3 -> U24 */
+ {
+ PIN_MCASP0_AXR14, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_CPSW2G0 -> RGMII1_RXC -> AD26 */
+ {
+ PIN_MCASP1_AXR3, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_CPSW2G0 -> RGMII1_RX_CTL -> AC25 */
+ {
+ PIN_MCASP0_AXR15, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_CPSW2G0 -> RGMII1_TD0 -> T25 */
+ {
+ PIN_MCASP0_AXR7, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_CPSW2G0 -> RGMII1_TD1 -> W24 */
+ {
+ PIN_MCASP0_AXR8, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_CPSW2G0 -> RGMII1_TD2 -> AA25 */
+ {
+ PIN_MCASP0_AXR9, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_CPSW2G0 -> RGMII1_TD3 -> V25 */
+ {
+ PIN_MCASP0_AXR10, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_CPSW2G0 -> RGMII1_TXC -> U25 */
+ {
+ PIN_MCASP1_AXR4, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_CPSW2G0 -> RGMII1_TX_CTL -> T24 */
+ {
+ PIN_MCASP0_AXR11, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gCpsw2gPinCfg[] =
+{
+ {0, TRUE, gCpsw2g0PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gGpio0PinCfg[] =
+{
+ /* main_gpio_pins_default -> GPIO0_0 -> AG24 */
+ {
+ PIN_EXTINTN, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* main_gpio_pins_default -> GPIO0_11 -> V23 */
+ {
+ PIN_GPIO0_11, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* main_gpio_pins_default -> GPIO0_12 -> T26 */
+ {
+ PIN_GPIO0_12, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* main_gpio_pins_default -> GPIO0_13 -> AD24 */
+ {
+ PIN_PMIC_WAKE0N, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* main_gpio_pins_default -> GPIO0_14 -> AB28 */
+ {
+ PIN_MCASP0_ACLKX, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* main_gpio_pins_default -> GPIO0_15 -> U27 */
+ {
+ PIN_MCASP0_AFSX, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* main_gpio_pins_default -> GPIO0_16 -> AC28 */
+ {
+ PIN_MCASP0_AXR0, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* main_gpio_pins_default -> GPIO0_17 -> Y26 */
+ {
+ PIN_MCASP0_AXR1, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* main_gpio_pins_default -> GPIO0_18 -> AB27 */
+ {
+ PIN_MCASP0_AXR2, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* main_gpio_pins_default -> GPIO0_23 -> AA26 */
+ {
+ PIN_MCASP2_AXR0, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* main_gpio_pins_default -> GPIO0_24 -> AC27 */
+ {
+ PIN_MCASP2_AXR1, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* main_gpio_pins_default -> GPIO0_27 -> V26 */
+ {
+ PIN_MCAN1_TX, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* main_gpio_pins_default -> GPIO0_28 -> R27 */
+ {
+ PIN_MCAN1_RX, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* main_gpio_pins_default -> GPIO0_29 -> R28 */
+ {
+ PIN_MCAN2_TX, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* main_gpio_pins_default -> GPIO0_30 -> Y25 */
+ {
+ PIN_MCAN2_RX, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* main_gpio_pins_default -> GPIO0_31 -> T27 */
+ {
+ PIN_MCASP0_AXR3, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* main_gpio_pins_default -> GPIO0_32 -> U26 */
+ {
+ PIN_MCASP0_AXR4, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* main_gpio_pins_default -> GPIO0_33 -> AA28 */
+ {
+ PIN_MCASP0_AXR5, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* main_gpio_pins_default -> GPIO0_34 -> AD27 */
+ {
+ PIN_MCASP0_AXR6, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* main_gpio_pins_default -> GPIO0_52 -> AF26 */
+ {
+ PIN_SPI0_CS1, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* main_gpio_pins_default -> GPIO0_58 -> AE25 */
+ {
+ PIN_TIMER_IO0, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* main_gpio_pins_default -> GPIO0_60 -> R22 */
+ {
+ PIN_MMC1_DAT3, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* main_gpio_pins_default -> GPIO0_61 -> R24 */
+ {
+ PIN_MMC1_DAT2, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gGpioPinCfg[] =
+{
+ {0, TRUE, gGpio0PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gI2c0PinCfg[] =
+{
+ /* main_I2C0 -> I2C0_SCL -> AH25 */
+ {
+ PIN_I2C0_SCL, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_I2C0 -> I2C0_SDA -> AE24 */
+ {
+ PIN_I2C0_SDA, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gI2c2PinCfg[] =
+{
+ /* main_I2C2 -> I2C2_SCL -> V27 */
+ {
+ PIN_MCASP1_AXR1, PIN_MODE(13) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_I2C2 -> I2C2_SDA -> W27 */
+ {
+ PIN_MCASP1_AXR2, PIN_MODE(13) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gI2c4PinCfg[] =
+{
+ /* main_I2C4 -> I2C4_SCL -> M23 */
+ {
+ PIN_MMC1_DAT0, PIN_MODE(10) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_I2C4 -> I2C4_SDA -> P24 */
+ {
+ PIN_MMC1_DAT1, PIN_MODE(10) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gI2c6PinCfg[] =
+{
+ /* main_I2C6 -> I2C6_SCL -> N24 */
+ {
+ PIN_MMC1_CMD, PIN_MODE(10) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_I2C6 -> I2C6_SDA -> P23 */
+ {
+ PIN_MMC1_CLK, PIN_MODE(10) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gI2cPinCfg[] =
+{
+ {0, TRUE, gI2c0PinCfg},
+ {2, TRUE, gI2c2PinCfg},
+ {4, TRUE, gI2c4PinCfg},
+ {6, TRUE, gI2c6PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gMcan2PinCfg[] =
+{
+ /* main_MCAN12 -> MCAN12_RX -> AC24 */
+ {
+ PIN_MCAN12_RX, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_MCAN12 -> MCAN12_TX -> W25 */
+ {
+ PIN_MCAN12_TX, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gMcan3PinCfg[] =
+{
+ /* main_MCAN13 -> MCAN13_RX -> AF28 */
+ {
+ PIN_MCAN13_RX, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_MCAN13 -> MCAN13_TX -> AE28 */
+ {
+ PIN_MCAN13_TX, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gMcan4PinCfg[] =
+{
+ /* main_MCAN14 -> MCAN14_RX -> W23 */
+ {
+ PIN_MCAN14_RX, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_MCAN14 -> MCAN14_TX -> AD25 */
+ {
+ PIN_MCAN14_TX, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gMcan5PinCfg[] =
+{
+ /* main_MCAN15 -> MCAN15_RX -> AA23 */
+ {
+ PIN_MCAN15_RX, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_MCAN15 -> MCAN15_TX -> Y24 */
+ {
+ PIN_MCAN15_TX, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gMcan6PinCfg[] =
+{
+ /* main_MCAN16 -> MCAN16_RX -> AB24 */
+ {
+ PIN_MCAN16_RX, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_MCAN16 -> MCAN16_TX -> Y28 */
+ {
+ PIN_MCAN16_TX, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gMcanPinCfg[] =
+{
+ {2, TRUE, gMcan2PinCfg},
+ {3, TRUE, gMcan3PinCfg},
+ {4, TRUE, gMcan4PinCfg},
+ {5, TRUE, gMcan5PinCfg},
+ {6, TRUE, gMcan6PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gMcu_adc0PinCfg[] =
+{
+ /* mcu_adc0 -> MCU_ADC0_AIN0 -> L25 */
+ {
+ PIN_MCU_ADC0_AIN0, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_adc0 -> MCU_ADC0_AIN1 -> K25 */
+ {
+ PIN_MCU_ADC0_AIN1, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_adc0 -> MCU_ADC0_AIN2 -> M24 */
+ {
+ PIN_MCU_ADC0_AIN2, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_adc0 -> MCU_ADC0_AIN3 -> L24 */
+ {
+ PIN_MCU_ADC0_AIN3, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_adc0 -> MCU_ADC0_AIN4 -> L27 */
+ {
+ PIN_MCU_ADC0_AIN4, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_adc0 -> MCU_ADC0_AIN5 -> K24 */
+ {
+ PIN_MCU_ADC0_AIN5, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_adc0 -> MCU_ADC0_AIN6 -> M27 */
+ {
+ PIN_MCU_ADC0_AIN6, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_adc0 -> MCU_ADC0_AIN7 -> M26 */
+ {
+ PIN_MCU_ADC0_AIN7, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gMcu_adc1PinCfg[] =
+{
+ /* mcu_adc1 -> MCU_ADC1_AIN0 -> P25 */
+ {
+ PIN_MCU_ADC1_AIN0, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_adc1 -> MCU_ADC1_AIN1 -> R25 */
+ {
+ PIN_MCU_ADC1_AIN1, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_adc1 -> MCU_ADC1_AIN2 -> P28 */
+ {
+ PIN_MCU_ADC1_AIN2, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_adc1 -> MCU_ADC1_AIN3 -> P27 */
+ {
+ PIN_MCU_ADC1_AIN3, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_adc1 -> MCU_ADC1_AIN4 -> N25 */
+ {
+ PIN_MCU_ADC1_AIN4, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_adc1 -> MCU_ADC1_AIN5 -> P26 */
+ {
+ PIN_MCU_ADC1_AIN5, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_adc1 -> MCU_ADC1_AIN6 -> N26 */
+ {
+ PIN_MCU_ADC1_AIN6, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_adc1 -> MCU_ADC1_AIN7 -> N27 */
+ {
+ PIN_MCU_ADC1_AIN7, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gMcu_adcPinCfg[] =
+{
+ {0, TRUE, gMcu_adc0PinCfg},
+ {1, TRUE, gMcu_adc1PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gMcu_cpsw2g0PinCfg[] =
+{
+ /* mcu_cpsw -> MCU_RGMII1_RD0 -> B22 */
+ {
+ PIN_MCU_RGMII1_RD0, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_cpsw -> MCU_RGMII1_RD1 -> B21 */
+ {
+ PIN_MCU_RGMII1_RD1, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_cpsw -> MCU_RGMII1_RD2 -> C22 */
+ {
+ PIN_MCU_RGMII1_RD2, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_cpsw -> MCU_RGMII1_RD3 -> D23 */
+ {
+ PIN_MCU_RGMII1_RD3, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_cpsw -> MCU_RGMII1_RXC -> D22 */
+ {
+ PIN_MCU_RGMII1_RXC, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_cpsw -> MCU_RGMII1_RX_CTL -> E23 */
+ {
+ PIN_MCU_RGMII1_RX_CTL, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_cpsw -> MCU_RGMII1_TD0 -> F23 */
+ {
+ PIN_MCU_RGMII1_TD0, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_cpsw -> MCU_RGMII1_TD1 -> G22 */
+ {
+ PIN_MCU_RGMII1_TD1, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_cpsw -> MCU_RGMII1_TD2 -> E21 */
+ {
+ PIN_MCU_RGMII1_TD2, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_cpsw -> MCU_RGMII1_TD3 -> E22 */
+ {
+ PIN_MCU_RGMII1_TD3, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_cpsw -> MCU_RGMII1_TXC -> F21 */
+ {
+ PIN_MCU_RGMII1_TXC, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_cpsw -> MCU_RGMII1_TX_CTL -> F22 */
+ {
+ PIN_MCU_RGMII1_TX_CTL, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gMcu_cpsw2gPinCfg[] =
+{
+ {0, TRUE, gMcu_cpsw2g0PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gMcu_i2c0PinCfg[] =
+{
+ /* mcu_i2c0 -> MCU_I2C0_SCL -> G24 */
+ {
+ PIN_MCU_I2C0_SCL, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_i2c0 -> MCU_I2C0_SDA -> J25 */
+ {
+ PIN_MCU_I2C0_SDA, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gMcu_i2c1PinCfg[] =
+{
+ /* mcu_i2c1 -> MCU_I2C1_SCL -> E25 */
+ {
+ PIN_WKUP_GPIO0_6, PIN_MODE(3) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_i2c1 -> MCU_I2C1_SDA -> F28 */
+ {
+ PIN_WKUP_GPIO0_7, PIN_MODE(3) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gMcu_i2cPinCfg[] =
+{
+ {0, TRUE, gMcu_i2c0PinCfg},
+ {1, TRUE, gMcu_i2c1PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gMcu_mcan0PinCfg[] =
+{
+ /* mcu_mcan0 -> MCU_MCAN0_RX -> E28 */
+ {
+ PIN_MCU_MCAN0_RX, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_mcan0 -> MCU_MCAN0_TX -> E27 */
+ {
+ PIN_MCU_MCAN0_TX, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gMcu_mcan1PinCfg[] =
+{
+ /* mcu_mcan1 -> MCU_MCAN1_RX -> F26 */
+ {
+ PIN_WKUP_GPIO0_5, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_mcan1 -> MCU_MCAN1_TX -> C23 */
+ {
+ PIN_WKUP_GPIO0_4, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gMcu_mcanPinCfg[] =
+{
+ {0, TRUE, gMcu_mcan0PinCfg},
+ {1, TRUE, gMcu_mcan1PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gMcu_mdio0PinCfg[] =
+{
+ /* mcu_mdio -> MCU_MDIO0_MDC -> A21 */
+ {
+ PIN_MCU_MDIO0_MDC, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_mdio -> MCU_MDIO0_MDIO -> A22 */
+ {
+ PIN_MCU_MDIO0_MDIO, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gMcu_mdioPinCfg[] =
+{
+ {0, TRUE, gMcu_mdio0PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gMcu_ospi0PinCfg[] =
+{
+ /* mcu_fss0_ospi0 -> MCU_OSPI0_CLK -> D19 */
+ {
+ PIN_MCU_OSPI0_CLK, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_fss0_ospi0 -> MCU_OSPI0_CSn0 -> F15 */
+ {
+ PIN_MCU_OSPI0_CSN0, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_fss0_ospi0 -> MCU_OSPI0_D0 -> C19 */
+ {
+ PIN_MCU_OSPI0_D0, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_fss0_ospi0 -> MCU_OSPI0_D1 -> F16 */
+ {
+ PIN_MCU_OSPI0_D1, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_fss0_ospi0 -> MCU_OSPI0_D2 -> G15 */
+ {
+ PIN_MCU_OSPI0_D2, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_fss0_ospi0 -> MCU_OSPI0_D3 -> F18 */
+ {
+ PIN_MCU_OSPI0_D3, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_fss0_ospi0 -> MCU_OSPI0_D4 -> E19 */
+ {
+ PIN_MCU_OSPI0_D4, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_fss0_ospi0 -> MCU_OSPI0_D5 -> G19 */
+ {
+ PIN_MCU_OSPI0_D5, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_fss0_ospi0 -> MCU_OSPI0_D6 -> F19 */
+ {
+ PIN_MCU_OSPI0_D6, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_fss0_ospi0 -> MCU_OSPI0_D7 -> F20 */
+ {
+ PIN_MCU_OSPI0_D7, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_fss0_ospi0 -> MCU_OSPI0_DQS -> E18 */
+ {
+ PIN_MCU_OSPI0_DQS, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_fss0_ospi0 -> MCU_OSPI0_RESET_OUT0 -> F14 */
+ {
+ PIN_MCU_OSPI0_CSN2, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gMcu_ospiPinCfg[] =
+{
+ {0, TRUE, gMcu_ospi0PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gMcu_spi0PinCfg[] =
+{
+ /* MCU_SPI0 -> MCU_SPI0_CLK -> B27 */
+ {
+ PIN_MCU_SPI0_CLK, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MCU_SPI0 -> MCU_SPI0_D0 -> D24 */
+ {
+ PIN_MCU_SPI0_D0, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MCU_SPI0 -> MCU_SPI0_D1 -> B25 */
+ {
+ PIN_MCU_SPI0_D1, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gMcu_spiPinCfg[] =
+{
+ {0, TRUE, gMcu_spi0PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gMcu_uart0PinCfg[] =
+{
+ /* mcu_uart0 -> MCU_UART0_RXD -> C24 */
+ {
+ PIN_WKUP_GPIO0_13, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* mcu_uart0 -> MCU_UART0_TXD -> C25 */
+ {
+ PIN_WKUP_GPIO0_12, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gMcu_uartPinCfg[] =
+{
+ {0, TRUE, gMcu_uart0PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gSpi0PinCfg[] =
+{
+ /* main_SPI0 -> SPI0_CLK -> AH27 */
+ {
+ PIN_SPI0_CLK, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_SPI0 -> SPI0_CS0 -> AE27 */
+ {
+ PIN_SPI0_CS0, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_SPI0 -> SPI0_D0 -> AG26 */
+ {
+ PIN_SPI0_D0, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_SPI0 -> SPI0_D1 -> AH26 */
+ {
+ PIN_SPI0_D1, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gSpiPinCfg[] =
+{
+ {0, TRUE, gSpi0PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gSystem0PinCfg[] =
+{
+ /* main_SYSTEM0 -> OBSCLK0 -> AG25 */
+ {
+ PIN_TIMER_IO1, PIN_MODE(2) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gSystemPinCfg[] =
+{
+ {0, TRUE, gSystem0PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gUart3PinCfg[] =
+{
+ /* main_UART3 -> UART3_RXD -> AB26 */
+ {
+ PIN_ECAP0_IN_APWM_OUT, PIN_MODE(14) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_UART3 -> UART3_TXD -> AD28 */
+ {
+ PIN_EXT_REFCLK1, PIN_MODE(14) | \
+ ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gUart2PinCfg[] =
+{
+ /* main_UART2 -> UART2_RXD -> W28 */
+ {
+ PIN_MCAN0_TX, PIN_MODE(11) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_UART2 -> UART2_TXD -> U28 */
+ {
+ PIN_MCAN0_RX, PIN_MODE(11) | \
+ ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gUart1PinCfg[] =
+{
+ /* main_UART1 -> UART1_RXD -> Y27 */
+ {
+ PIN_MCASP2_ACLKX, PIN_MODE(11) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* main_UART1 -> UART1_TXD -> AA27 */
+ {
+ PIN_MCASP2_AFSX, PIN_MODE(11) | \
+ ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gUartPinCfg[] =
+{
+ {3, TRUE, gUart3PinCfg},
+ {2, TRUE, gUart2PinCfg},
+ {1, TRUE, gUart1PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gWkup_gpio0PinCfg[] =
+{
+ /* WKUP_GPIO0 -> WKUP_GPIO0_0 -> D26 */
+ {
+ PIN_WKUP_GPIO0_0, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_1 -> E24 */
+ {
+ PIN_WKUP_GPIO0_1, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_2 -> C28 */
+ {
+ PIN_WKUP_GPIO0_2, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_3 -> C27 */
+ {
+ PIN_WKUP_GPIO0_3, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_8 -> F24 */
+ {
+ PIN_WKUP_GPIO0_8, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_9 -> H26 */
+ {
+ PIN_WKUP_GPIO0_9, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_10 -> F27 */
+ {
+ PIN_WKUP_GPIO0_10, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_11 -> F25 */
+ {
+ PIN_WKUP_GPIO0_11, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_14 -> B24 */
+ {
+ PIN_WKUP_GPIO0_14, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_15 -> D25 */
+ {
+ PIN_WKUP_GPIO0_15, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_17 -> E20 */
+ {
+ PIN_MCU_OSPI0_LBCLKO, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_28 -> G17 */
+ {
+ PIN_MCU_OSPI0_CSN1, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_30 -> F17 */
+ {
+ PIN_MCU_OSPI0_CSN3, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_31 -> A19 */
+ {
+ PIN_MCU_OSPI1_CLK, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_32 -> B20 */
+ {
+ PIN_MCU_OSPI1_LBCLKO, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_33 -> B19 */
+ {
+ PIN_MCU_OSPI1_DQS, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_34 -> D21 */
+ {
+ PIN_MCU_OSPI1_D0, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_35 -> G20 */
+ {
+ PIN_MCU_OSPI1_D1, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_36 -> C20 */
+ {
+ PIN_MCU_OSPI1_D2, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_37 -> A20 */
+ {
+ PIN_MCU_OSPI1_D3, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_38 -> D20 */
+ {
+ PIN_MCU_OSPI1_CSN0, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_39 -> C21 */
+ {
+ PIN_MCU_OSPI1_CSN1, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_49 -> K26 */
+ {
+ PIN_WKUP_GPIO0_49, PIN_MODE(7) | \
+ ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_56 -> G27 */
+ {
+ PIN_WKUP_GPIO0_56, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_57 -> J26 */
+ {
+ PIN_WKUP_GPIO0_57, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_66 -> G25 */
+ {
+ PIN_WKUP_GPIO0_66, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_67 -> J27 */
+ {
+ PIN_WKUP_GPIO0_67, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_70 -> B26 */
+ {
+ PIN_MCU_SPI0_CS0, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ /* WKUP_GPIO0 -> WKUP_GPIO0_88 -> G26 */
+ {
+ PIN_PMIC_POWER_EN1, PIN_MODE(7) | \
+ ((PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE & ~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gWkup_gpioPinCfg[] =
+{
+ {0, TRUE, gWkup_gpio0PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gWkup_i2c0PinCfg[] =
+{
+ /* wakeup_i2c0 -> WKUP_I2C0_SCL -> H24 */
+ {
+ PIN_WKUP_I2C0_SCL, PIN_MODE(0) | \
+ ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
+ },
+ /* wakeup_i2c0 -> WKUP_I2C0_SDA -> H27 */
+ {
+ PIN_WKUP_I2C0_SDA, PIN_MODE(0) | \
+ ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gWkup_i2cPinCfg[] =
+{
+ {0, TRUE, gWkup_i2c0PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gWkup_system0PinCfg[] =
+{
+ /* MyWKUP_SYSTEM1 -> MCU_RESETSTATz -> A23 */
+ {
+ PIN_MCU_RESETSTATZ, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gWkup_systemPinCfg[] =
+{
+ {0, TRUE, gWkup_system0PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gWkup_uart0PinCfg[] =
+{
+ /* wakeup_uart0 -> WKUP_UART0_RXD -> D28 */
+ {
+ PIN_WKUP_UART0_RXD, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* wakeup_uart0 -> WKUP_UART0_TXD -> D27 */
+ {
+ PIN_WKUP_UART0_TXD, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gWkup_uartPinCfg[] =
+{
+ {0, TRUE, gWkup_uart0PinCfg},
+ {PINMUX_END}
+};
+
+
+pinmuxBoardCfg_t gJ721S2_MainPinmuxData[] =
+{
+ {0, gCpsw2gPinCfg},
+ {1, gGpioPinCfg},
+ {2, gI2cPinCfg},
+ {3, gMcanPinCfg},
+ {4, gSpiPinCfg},
+ {5, gSystemPinCfg},
+ {6, gUartPinCfg},
+ {PINMUX_END}
+};
+
+pinmuxBoardCfg_t gJ721S2_WkupPinmuxData[] =
+{
+ {0, gMcu_adcPinCfg},
+ {1, gMcu_cpsw2gPinCfg},
+ {2, gMcu_i2cPinCfg},
+ {3, gMcu_mcanPinCfg},
+ {4, gMcu_mdioPinCfg},
+ {5, gMcu_ospiPinCfg},
+ {6, gMcu_spiPinCfg},
+ {7, gMcu_uartPinCfg},
+ {8, gWkup_gpioPinCfg},
+ {9, gWkup_i2cPinCfg},
+ {10, gWkup_systemPinCfg},
+ {11, gWkup_uartPinCfg},
+ {PINMUX_END}
+};
diff --git a/packages/ti/board/src/j721s2_evm/include/board_ddrRegInit.h b/packages/ti/board/src/j721s2_evm/include/board_ddrRegInit.h
old mode 100644
new mode 100755
index 1a7d7bd6..7c0513a6
--- a/packages/ti/board/src/j721s2_evm/include/board_ddrRegInit.h
+++ b/packages/ti/board/src/j721s2_evm/include/board_ddrRegInit.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2021, Texas Instruments Incorporated
+/* Copyright (c) 2019, Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -28,11 +28,11 @@
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/*
- * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.7.0
- * This file was generated on 10/25/2021
+ * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.9.1
+ * This file was generated on 04/20/2023
*/
-#define DDRSS_PLL_FHS_CNT 10U
+#define DDRSS_PLL_FHS_CNT 6
#define DDRSS_PLL_FREQUENCY_0 27500000
#define DDRSS_PLL_FREQUENCY_1 1066500000
#define DDRSS_PLL_FREQUENCY_2 1066500000
@@ -42,7 +42,7 @@
#define DDRSS_PHY_REG_INIT_COUNT (1423U)
#define MULTI_DDR_CFG_INTRLV_GRAN 0
-#define MULTI_DDR_CFG_INTRLV_SIZE 11
+#define MULTI_DDR_CFG_INTRLV_SIZE 7
#define MULTI_DDR_CFG_ECC_ENABLE 0
#define MULTI_DDR_CFG_HYBRID_SELECT 0
#define MULTI_DDR_CFG_EMIFS_ACTIVE 3
@@ -85,12 +85,12 @@ uint32_t DDRSS0_ctlReg[] = {
0x040C0000U,
0x12481248U,
0x00050804U,
- 0x09040008U,
- 0x15000204U,
- 0x1760008BU,
- 0x1500422BU,
- 0x1760008BU,
- 0x2000422BU,
+ 0x09040007U,
+ 0x11000203U,
+ 0x175C0083U,
+ 0x11004227U,
+ 0x175C0083U,
+ 0x20004227U,
0x000A0A09U,
0x0400078AU,
0x1E161104U,
@@ -98,38 +98,38 @@ uint32_t DDRSS0_ctlReg[] = {
0x1E161110U,
0x10012458U,
0x02030410U,
- 0x2C040500U,
- 0x08292C29U,
+ 0x28040500U,
+ 0x08292829U,
0x14000E0AU,
0x04010A0AU,
0x01010004U,
- 0x04545408U,
- 0x04313104U,
- 0x00003131U,
+ 0x04505007U,
+ 0x032D2D03U,
+ 0x00002D2DU,
0x00010100U,
0x03010000U,
- 0x00001508U,
+ 0x00001008U,
0x000000CEU,
- 0x0000032BU,
+ 0x00000256U,
0x00002073U,
- 0x0000032BU,
+ 0x00000256U,
0x00002073U,
0x00000005U,
- 0x00050000U,
- 0x00CB0012U,
- 0x00CB0408U,
+ 0x00040000U,
+ 0x00950012U,
+ 0x00950408U,
0x00400408U,
0x00120103U,
0x00100005U,
- 0x2F080010U,
- 0x0505012FU,
+ 0x2B080010U,
+ 0x0505012BU,
0x0401030AU,
0x041E100BU,
0x100B0401U,
0x0001041EU,
- 0x00160016U,
- 0x033B033BU,
- 0x033B033BU,
+ 0x00100010U,
+ 0x02660266U,
+ 0x02660266U,
0x03050505U,
0x03010303U,
0x200B100BU,
@@ -226,15 +226,15 @@ uint32_t DDRSS0_ctlReg[] = {
0x3FF40084U,
0x33003FF4U,
0x00003333U,
- 0x56000000U,
- 0x27270056U,
+ 0x35000000U,
+ 0x27270035U,
0x0F0F0000U,
0x16000000U,
0x00841616U,
0x3FF43FF4U,
0x33333300U,
0x00000000U,
- 0x00565600U,
+ 0x00353500U,
0x00002727U,
0x00000F0FU,
0x16161600U,
@@ -277,17 +277,17 @@ uint32_t DDRSS0_ctlReg[] = {
0x00000000U,
0x15110000U,
0x00040C18U,
+ 0xF000C000U,
+ 0x0000F000U,
0x00000000U,
0x00000000U,
+ 0xC0000000U,
+ 0xF000F000U,
0x00000000U,
0x00000000U,
0x00000000U,
- 0x00000000U,
- 0x00000000U,
- 0x00000000U,
- 0x00000000U,
- 0x00000000U,
- 0x00000000U,
+ 0xF000C000U,
+ 0x0000F000U,
0x00000000U,
0x00000000U,
0x00030000U,
@@ -315,18 +315,18 @@ uint32_t DDRSS0_ctlReg[] = {
0x00000040U,
0x006B0003U,
0x0100006BU,
- 0x00000000U,
- 0x00000000U,
+ 0x01010101U,
+ 0x01010000U,
0x00000202U,
- 0x00001FFFU,
- 0x3FFF2000U,
- 0x03FF0000U,
- 0x000103FFU,
+ 0x00000FFFU,
+ 0xFFFFFFFFU,
+ 0x01FF0000U,
+ 0x000001FFU,
0x0FFF0B00U,
0x01010001U,
0x01010101U,
0x01180101U,
- 0x00030000U,
+ 0x00010000U,
0x00000000U,
0x00000000U,
0x00000000U,
@@ -335,7 +335,7 @@ uint32_t DDRSS0_ctlReg[] = {
0x00000000U,
0x00000000U,
0x00040101U,
- 0x04010100U,
+ 0x00000100U,
0x00000000U,
0x00000000U,
0x03030300U,
@@ -524,7 +524,7 @@ uint32_t DDRSS0_phyIndepReg[] = {
0x00000000U,
0x00000007U,
0x00010002U,
- 0x0800000FU,
+ 0x08000005U,
0x00000103U,
0x00000005U,
0x00000000U,
@@ -539,7 +539,7 @@ uint32_t DDRSS0_phyIndepReg[] = {
0x00010100U,
0x00280A00U,
0x00000000U,
- 0x0F000000U,
+ 0x05000000U,
0x00003200U,
0x00000000U,
0x00000000U,
@@ -555,7 +555,7 @@ uint32_t DDRSS0_phyIndepReg[] = {
0x000000B5U,
0x00000000U,
0x00000000U,
- 0x000F0F00U,
+ 0x00050500U,
0x0000001BU,
0x000007D0U,
0x00000300U,
@@ -565,7 +565,7 @@ uint32_t DDRSS0_phyIndepReg[] = {
0x00010101U,
0x00000000U,
0x00030000U,
- 0x0F000000U,
+ 0x05000000U,
0x00000017U,
0x00000000U,
0x00000000U,
@@ -577,13 +577,13 @@ uint32_t DDRSS0_phyIndepReg[] = {
0x00000000U,
0x00000000U,
0x00000100U,
- 0x0001010FU,
+ 0x00010105U,
0x00340000U,
0x00000000U,
0x00000000U,
0x0000FFFFU,
0x00000000U,
- 0x00080000U,
+ 0x00080100U,
0x02000200U,
0x01000100U,
0x01000000U,
@@ -679,11 +679,11 @@ uint32_t DDRSS0_phyIndepReg[] = {
0x00020064U,
0x02000200U,
0x48120C04U,
- 0x00154812U,
+ 0x00104812U,
0x000000CEU,
- 0x0000032BU,
+ 0x00000256U,
0x00002073U,
- 0x0000032BU,
+ 0x00000256U,
0x04002073U,
0x01010404U,
0x00001501U,
@@ -728,16 +728,16 @@ uint32_t DDRSS0_phyIndepReg[] = {
0x00003600U,
0x3212005BU,
0x09000301U,
- 0x04010504U,
+ 0x04010503U,
0x040006C9U,
0x0A032001U,
- 0x2C31110AU,
+ 0x282D110AU,
0x00002918U,
- 0x6001071CU,
+ 0x5C01071CU,
0x1E202008U,
- 0x2C311116U,
+ 0x282D1116U,
0x00002918U,
- 0x6001071CU,
+ 0x5C01071CU,
0x1E202008U,
0x00019C16U,
0x00001018U,
@@ -745,23 +745,23 @@ uint32_t DDRSS0_phyIndepReg[] = {
0x000288FCU,
0x000040E6U,
0x000288FCU,
- 0x033B0016U,
- 0x0303033BU,
+ 0x02660010U,
+ 0x03030266U,
0x002AF803U,
0x0001ADAFU,
0x00000005U,
0x0000006EU,
- 0x00000016U,
+ 0x00000010U,
0x000681C8U,
0x0001ADAFU,
0x00000005U,
0x000010A9U,
- 0x0000033BU,
+ 0x00000266U,
0x000681C8U,
0x0001ADAFU,
0x00000005U,
0x000010A9U,
- 0x0100033BU,
+ 0x01000266U,
0x00370040U,
0x00010008U,
0x08550040U,
@@ -787,27 +787,27 @@ uint32_t DDRSS0_phyIndepReg[] = {
0x00000000U,
0x00330084U,
0x00160000U,
- 0x56333FF4U,
+ 0x35333FF4U,
0x00160F27U,
- 0x56333FF4U,
+ 0x35333FF4U,
0x00160F27U,
0x00330084U,
0x00160000U,
- 0x56333FF4U,
+ 0x35333FF4U,
0x00160F27U,
- 0x56333FF4U,
+ 0x35333FF4U,
0x00160F27U,
0x00330084U,
0x00160000U,
- 0x56333FF4U,
+ 0x35333FF4U,
0x00160F27U,
- 0x56333FF4U,
+ 0x35333FF4U,
0x00160F27U,
0x00330084U,
0x00160000U,
- 0x56333FF4U,
+ 0x35333FF4U,
0x00160F27U,
- 0x56333FF4U,
+ 0x35333FF4U,
0x00160F27U,
0x00000000U,
};
@@ -845,7 +845,7 @@ uint32_t DDRSS0_phyReg[] = {
0x00000808U,
0x0F000000U,
0x00000F0FU,
- 0x10200000U,
+ 0x10400000U,
0x0C002006U,
0x00000000U,
0x00000000U,
@@ -1101,7 +1101,7 @@ uint32_t DDRSS0_phyReg[] = {
0x00000808U,
0x0F000000U,
0x00000F0FU,
- 0x10200000U,
+ 0x10400000U,
0x0C002006U,
0x00000000U,
0x00000000U,
@@ -1357,7 +1357,7 @@ uint32_t DDRSS0_phyReg[] = {
0x00000808U,
0x0F000000U,
0x00000F0FU,
- 0x10200000U,
+ 0x10400000U,
0x0C002006U,
0x00000000U,
0x00000000U,
@@ -1613,7 +1613,7 @@ uint32_t DDRSS0_phyReg[] = {
0x00000808U,
0x0F000000U,
0x00000F0FU,
- 0x10200000U,
+ 0x10400000U,
0x0C002006U,
0x00000000U,
0x00000000U,
@@ -2123,7 +2123,7 @@ uint32_t DDRSS0_phyReg[] = {
0x01200F02U,
0x00194280U,
0x00000004U,
- 0x00052000U,
+ 0x00042000U,
0x00000000U,
0x00000000U,
0x00000000U,
@@ -2277,11 +2277,11 @@ uint32_t DDRSS1_ctlReg[] = {
0x12481248U,
0x00050804U,
0x09040008U,
- 0x15000204U,
- 0x1760008BU,
- 0x1500422BU,
- 0x1760008BU,
- 0x2000422BU,
+ 0x11000204U,
+ 0x175C0083U,
+ 0x11004227U,
+ 0x175C0083U,
+ 0x20004227U,
0x000A0A09U,
0x0400078AU,
0x1E161104U,
@@ -2289,38 +2289,38 @@ uint32_t DDRSS1_ctlReg[] = {
0x1E161110U,
0x10012458U,
0x02030410U,
- 0x2C040500U,
- 0x08292C29U,
+ 0x28040500U,
+ 0x08292829U,
0x14000E0AU,
0x04010A0AU,
0x01010004U,
- 0x04545408U,
- 0x04313104U,
- 0x00003131U,
+ 0x04505008U,
+ 0x042D2D04U,
+ 0x00002D2DU,
0x00010100U,
0x03010000U,
- 0x00001508U,
+ 0x00001008U,
0x000000CEU,
- 0x0000032BU,
+ 0x00000256U,
0x00002073U,
- 0x0000032BU,
+ 0x00000256U,
0x00002073U,
0x00000005U,
- 0x00050000U,
- 0x00CB0012U,
- 0x00CB0408U,
+ 0x00040000U,
+ 0x00950012U,
+ 0x00950408U,
0x00400408U,
0x00120103U,
0x00100005U,
- 0x2F080010U,
- 0x0505012FU,
+ 0x2B080010U,
+ 0x0505012BU,
0x0401030AU,
0x041E100BU,
0x100B0401U,
0x0001041EU,
- 0x00160016U,
- 0x033B033BU,
- 0x033B033BU,
+ 0x00100010U,
+ 0x02660266U,
+ 0x02660266U,
0x03050505U,
0x03010303U,
0x200B100BU,
@@ -2417,15 +2417,15 @@ uint32_t DDRSS1_ctlReg[] = {
0x3FF40084U,
0x33003FF4U,
0x00003333U,
- 0x56000000U,
- 0x27270056U,
+ 0x35000000U,
+ 0x27270035U,
0x0F0F0000U,
0x16000000U,
0x00841616U,
0x3FF43FF4U,
0x33333300U,
0x00000000U,
- 0x00565600U,
+ 0x00353500U,
0x00002727U,
0x00000F0FU,
0x16161600U,
@@ -2468,17 +2468,17 @@ uint32_t DDRSS1_ctlReg[] = {
0x00000000U,
0x15110000U,
0x00040C18U,
+ 0xF000C000U,
+ 0x0000F000U,
0x00000000U,
0x00000000U,
+ 0xC0000000U,
+ 0xF000F000U,
0x00000000U,
0x00000000U,
0x00000000U,
- 0x00000000U,
- 0x00000000U,
- 0x00000000U,
- 0x00000000U,
- 0x00000000U,
- 0x00000000U,
+ 0xF000C000U,
+ 0x0000F000U,
0x00000000U,
0x00000000U,
0x00030000U,
@@ -2506,18 +2506,18 @@ uint32_t DDRSS1_ctlReg[] = {
0x00000040U,
0x006B0003U,
0x0100006BU,
- 0x00000000U,
- 0x00000000U,
+ 0x01010101U,
+ 0x01010000U,
0x00000202U,
- 0x00001FFFU,
- 0x3FFF2000U,
- 0x03FF0000U,
- 0x000103FFU,
+ 0x00000FFFU,
+ 0xFFFFFFFFU,
+ 0x01FF0000U,
+ 0x000001FFU,
0x0FFF0B00U,
0x01010001U,
0x01010101U,
0x01180101U,
- 0x00030000U,
+ 0x00010000U,
0x00000000U,
0x00000000U,
0x00000000U,
@@ -2526,7 +2526,7 @@ uint32_t DDRSS1_ctlReg[] = {
0x00000000U,
0x00000000U,
0x00040101U,
- 0x04010100U,
+ 0x00000100U,
0x00000000U,
0x00000000U,
0x03030300U,
@@ -2715,7 +2715,7 @@ uint32_t DDRSS1_phyIndepReg[] = {
0x00000000U,
0x00000007U,
0x00010002U,
- 0x0800000FU,
+ 0x08000005U,
0x00000103U,
0x00000005U,
0x00000000U,
@@ -2730,7 +2730,7 @@ uint32_t DDRSS1_phyIndepReg[] = {
0x00010100U,
0x00280A00U,
0x00000000U,
- 0x0F000000U,
+ 0x05000000U,
0x00003200U,
0x00000000U,
0x00000000U,
@@ -2746,7 +2746,7 @@ uint32_t DDRSS1_phyIndepReg[] = {
0x000000B5U,
0x00000000U,
0x00000000U,
- 0x000F0F00U,
+ 0x00050500U,
0x0000001BU,
0x000007D0U,
0x00000300U,
@@ -2756,7 +2756,7 @@ uint32_t DDRSS1_phyIndepReg[] = {
0x00010101U,
0x00000000U,
0x00030000U,
- 0x0F000000U,
+ 0x05000000U,
0x00000017U,
0x00000000U,
0x00000000U,
@@ -2768,13 +2768,13 @@ uint32_t DDRSS1_phyIndepReg[] = {
0x00000000U,
0x00000000U,
0x00000100U,
- 0x0001010FU,
+ 0x00010105U,
0x00340000U,
0x00000000U,
0x00000000U,
0x0000FFFFU,
0x00000000U,
- 0x00080000U,
+ 0x00080100U,
0x02000200U,
0x01000100U,
0x01000000U,
@@ -2870,11 +2870,11 @@ uint32_t DDRSS1_phyIndepReg[] = {
0x00020064U,
0x02000200U,
0x48120C04U,
- 0x00154812U,
+ 0x00104812U,
0x000000CEU,
- 0x0000032BU,
+ 0x00000256U,
0x00002073U,
- 0x0000032BU,
+ 0x00000256U,
0x04002073U,
0x01010404U,
0x00001501U,
@@ -2922,13 +2922,13 @@ uint32_t DDRSS1_phyIndepReg[] = {
0x04010504U,
0x040006C9U,
0x0A032001U,
- 0x2C31110AU,
+ 0x282D110AU,
0x00002918U,
- 0x6001071CU,
+ 0x5C01071CU,
0x1E202008U,
- 0x2C311116U,
+ 0x282D1116U,
0x00002918U,
- 0x6001071CU,
+ 0x5C01071CU,
0x1E202008U,
0x00019C16U,
0x00001018U,
@@ -2936,23 +2936,23 @@ uint32_t DDRSS1_phyIndepReg[] = {
0x000288FCU,
0x000040E6U,
0x000288FCU,
- 0x033B0016U,
- 0x0303033BU,
+ 0x02660010U,
+ 0x03030266U,
0x002AF803U,
0x0001ADAFU,
0x00000005U,
0x0000006EU,
- 0x00000016U,
+ 0x00000010U,
0x000681C8U,
0x0001ADAFU,
0x00000005U,
0x000010A9U,
- 0x0000033BU,
+ 0x00000266U,
0x000681C8U,
0x0001ADAFU,
0x00000005U,
0x000010A9U,
- 0x0100033BU,
+ 0x01000266U,
0x00370040U,
0x00010008U,
0x08550040U,
@@ -2978,27 +2978,27 @@ uint32_t DDRSS1_phyIndepReg[] = {
0x00000000U,
0x00330084U,
0x00160000U,
- 0x56333FF4U,
+ 0x35333FF4U,
0x00160F27U,
- 0x56333FF4U,
+ 0x35333FF4U,
0x00160F27U,
0x00330084U,
0x00160000U,
- 0x56333FF4U,
+ 0x35333FF4U,
0x00160F27U,
- 0x56333FF4U,
+ 0x35333FF4U,
0x00160F27U,
0x00330084U,
0x00160000U,
- 0x56333FF4U,
+ 0x35333FF4U,
0x00160F27U,
- 0x56333FF4U,
+ 0x35333FF4U,
0x00160F27U,
0x00330084U,
0x00160000U,
- 0x56333FF4U,
+ 0x35333FF4U,
0x00160F27U,
- 0x56333FF4U,
+ 0x35333FF4U,
0x00160F27U,
0x00000000U,
};
@@ -3036,7 +3036,7 @@ uint32_t DDRSS1_phyReg[] = {
0x00000808U,
0x0F000000U,
0x00000F0FU,
- 0x10200000U,
+ 0x10400000U,
0x0C002006U,
0x00000000U,
0x00000000U,
@@ -3292,7 +3292,7 @@ uint32_t DDRSS1_phyReg[] = {
0x00000808U,
0x0F000000U,
0x00000F0FU,
- 0x10200000U,
+ 0x10400000U,
0x0C002006U,
0x00000000U,
0x00000000U,
@@ -3548,7 +3548,7 @@ uint32_t DDRSS1_phyReg[] = {
0x00000808U,
0x0F000000U,
0x00000F0FU,
- 0x10200000U,
+ 0x10400000U,
0x0C002006U,
0x00000000U,
0x00000000U,
@@ -3804,7 +3804,7 @@ uint32_t DDRSS1_phyReg[] = {
0x00000808U,
0x0F000000U,
0x00000F0FU,
- 0x10200000U,
+ 0x10400000U,
0x0C002006U,
0x00000000U,
0x00000000U,
@@ -4314,7 +4314,7 @@ uint32_t DDRSS1_phyReg[] = {
0x01200F02U,
0x00194280U,
0x00000004U,
- 0x00052000U,
+ 0x00042000U,
0x00000000U,
0x00000000U,
0x00000000U,
@@ -4429,6 +4429,7 @@ uint32_t DDRSS1_phyReg[] = {
0x20040006U,
};
+
uint16_t DDRSS_ctlRegNum[] = {
0,
1,
diff --git a/packages/ti/board/src/j721s2_evm/include/board_internal.h b/packages/ti/board/src/j721s2_evm/include/board_internal.h
old mode 100644
new mode 100755
index 0134e8b1..f485683c
--- a/packages/ti/board/src/j721s2_evm/include/board_internal.h
+++ b/packages/ti/board/src/j721s2_evm/include/board_internal.h
@@ -58,8 +58,8 @@ extern "C" {
#define BOARD_I2C_PORT_CNT (I2C_HWIP_MAX_CNT)
-#undef ENABLE_LOGS
-
+#define ENABLE_LOGS
+#undef BOARD_DEBUG_LOG
#if !defined(BOARD_DEBUG_LOG)
#if defined(ENABLE_LOGS)
#define BOARD_DEBUG_LOG UART_printf
diff --git a/packages/ti/boot/sbl/board/k3/sbl_main.c b/packages/ti/boot/sbl/board/k3/sbl_main.c
index 19b07361..1f72d0dd 100755
--- a/packages/ti/boot/sbl/board/k3/sbl_main.c
+++ b/packages/ti/boot/sbl/board/k3/sbl_main.c
@@ -428,18 +428,21 @@ int main()
#endif
#if !defined(BOOT_PERF)
+#if 0
SBL_log(SBL_LOG_MAX, "Copying EEPROM content to DDR ... \n");
if (CSL_PASS != Board_initBoardIdData((uint8_t *) EEPROM_DATA_DDR_ADDRESS))
{
SBL_log(SBL_LOG_MAX, "\n Failed to copy EEPROM Data !! \n");
}
SBL_log(SBL_LOG_MAX, "EEPROM Data Copy Done.\n");
+#endif
#endif
/* Defined separate target for sbl uart i.e sbl_hsm_boot_uart_img to boot HSM core
For MMCSD, OSPI NOR, OSPI NAND boot HSM core will be boot in with the normal sbl targets i.e
sbl_mmcsd_img_hs, sbl_ospi_img_hs and sbl_ospi_nand_img_hs if hsm.bin is present else SBL proceeds to boot appimage */
#if ((defined(SOC_J721S2) || defined(SOC_J784S4)) && (defined(BOOT_OSPI) || defined(BOOT_MMCSD) || (defined(BOOT_UART) && defined(SECURE_HSM_BOOT))))
+#if 0
SBL_log(SBL_LOG_MAX, "Booting HSM core ... \n");
if (SBL_loadAndAuthHsmBinary() == CSL_PASS)
{
@@ -449,6 +452,7 @@ int main()
{
SBL_log(SBL_LOG_MAX, "Failed to boot HSM core !! \n");
}
+#endif
#endif
#if !defined(BOOT_PERF)
/* Change parent clock of input muxed clock to A72 core.
diff --git a/packages/ti/boot/sbl/sbl_component.mk b/packages/ti/boot/sbl/sbl_component.mk
old mode 100644
new mode 100755
index 4e591e22..0e093290
--- a/packages/ti/boot/sbl/sbl_component.mk
+++ b/packages/ti/boot/sbl/sbl_component.mk
@@ -1122,7 +1122,7 @@ export sbl_hsm_boot_uart_img_hs_COMP_LIST = sbl_hsm_boot_uart_img_hs
sbl_hsm_boot_uart_img_hs_RELPATH = ti/boot/sbl/board/k3
sbl_hsm_boot_uart_img_hs_CUSTOM_BINPATH = $(PDK_SBL_COMP_PATH)/binary/$(BOARD)_hs/uart/bin
sbl_hsm_boot_uart_img_hs_PATH = $(PDK_SBL_COMP_PATH)/board/k3
-export sbl_hsm_boot_uart_img_hs_MAKEFILE = -f$(PDK_SBL_COMP_PATH)/build/sbl_img.mk BOOTMODE=uart SBL_USE_DMA=yes BUILD_HS=yes SECURE_HSM_BOOT=yes
+export sbl_hsm_boot_uart_img_hs_MAKEFILE = -f$(PDK_SBL_COMP_PATH)/build/sbl_img.mk BOOTMODE=uart SBL_USE_DMA=yes BUILD_HS=yes
export sbl_hsm_boot_uart_img_hs_SBL_CERT_KEY=$(SBL_CERT_KEY_HS)
export sbl_hsm_boot_uart_img_hs_BOARD_DEPENDENCY = yes
export sbl_hsm_boot_uart_img_hs_SOC_DEPENDENCY = yes
@@ -1138,7 +1138,7 @@ export sbl_hsm_boot_uart_img_COMP_LIST = sbl_hsm_boot_uart_img
sbl_hsm_boot_uart_img_RELPATH = ti/boot/sbl/board/k3
sbl_hsm_boot_uart_img_CUSTOM_BINPATH = $(PDK_SBL_COMP_PATH)/binary/$(BOARD)/uart/bin
sbl_hsm_boot_uart_img_PATH = $(PDK_SBL_COMP_PATH)/board/k3
-export sbl_hsm_boot_uart_img_MAKEFILE = -f$(PDK_SBL_COMP_PATH)/build/sbl_img.mk BOOTMODE=uart SBL_USE_DMA=yes BUILD_HS=no SECURE_HSM_BOOT=yes
+export sbl_hsm_boot_uart_img_MAKEFILE = -f$(PDK_SBL_COMP_PATH)/build/sbl_img.mk BOOTMODE=uart SBL_USE_DMA=yes BUILD_HS=no
export sbl_hsm_boot_uart_img_SBL_CERT_KEY=$(SBL_CERT_KEY)
export sbl_hsm_boot_uart_img_BOARD_DEPENDENCY = yes
export sbl_hsm_boot_uart_img_SOC_DEPENDENCY = yes
@@ -1361,7 +1361,7 @@ export sbl_boot_multicore_xip_entry_SBL_APPIMAGEGEN
# SBL log level
# no logs = 0, only errors =1, normal logs = 2, all logs = 3
-SBL_CFLAGS += -DSBL_LOG_LEVEL=2
+SBL_CFLAGS += -DSBL_LOG_LEVEL=5
SBL_CFLAGS += -DSBL_ENABLE_PLL
SBL_CFLAGS += -DSBL_ENABLE_CLOCKS
@@ -1451,7 +1451,7 @@ endif
# If enabled the SBL image is built for running on VLAB simulation.
#SBL_CFLAGS += -DVLAB_SIM
-
+#SBL_CFLAGS += -DBOOT_PERF
###########END BOOT PERF KNOBS#############
# Example - Building Custom SBL Images
@@ -1460,8 +1460,8 @@ endif
CUST_SBL_TEST_SOCS = j721e j7200 j721s2 j784s4
CUST_SBL_TEST_BOARDS = j721e_evm j7200_evm j721s2_evm j784s4_evm
ifeq ($(SOC),$(filter $(SOC), j721e j7200 j721s2 j784s4))
-CUST_SBL_TEST_FLAGS =" -DSBL_LOG_LEVEL=1 -DSBL_SCRATCH_MEM_START=0xB8000000 -DSBL_SCRATCH_MEM_SIZE=0x4000000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_ENABLE_DDR -DSBL_SKIP_MCU_RESET -DBOOT_OSPI ${OCM_RAT_STRING}"
-CUST_SBL_BOOT_PERF_TEST_FLAGS =" -DSBL_LOG_LEVEL=1 -DSBL_SCRATCH_MEM_START=0x41cc0000 -DSBL_SCRATCH_MEM_SIZE=0x40000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_SKIP_MCU_RESET -DBOOT_OSPI -DSBL_HLOS_OWNS_FLASH -DSBL_SKIP_LATE_INIT -DSBL_USE_MCU_DOMAIN_ONLY"
+CUST_SBL_TEST_FLAGS =" -DSBL_LOG_LEVEL=5 -DSBL_SCRATCH_MEM_START=0xB8000000 -DSBL_SCRATCH_MEM_SIZE=0x4000000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_ENABLE_DDR -DSBL_SKIP_MCU_RESET -DBOOT_OSPI ${OCM_RAT_STRING}"
+CUST_SBL_BOOT_PERF_TEST_FLAGS =" -DSBL_LOG_LEVEL=5 -DSBL_SCRATCH_MEM_START=0x41cc0000 -DSBL_SCRATCH_MEM_SIZE=0x40000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_SKIP_MCU_RESET -DBOOT_OSPI -DSBL_HLOS_OWNS_FLASH -DSBL_SKIP_LATE_INIT -DSBL_USE_MCU_DOMAIN_ONLY "
# NOTE: To measure Early CAN response uncomment below line and comment above line
#CUST_SBL_BOOT_PERF_TEST_FLAGS =" -DSBL_LOG_LEVEL=1 -DSBL_SCRATCH_MEM_START=0x41cc0000 -DSBL_SCRATCH_MEM_SIZE=0x40000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_SKIP_MCU_RESET -DBOOT_OSPI -DSBL_HLOS_OWNS_FLASH -DSBL_SKIP_LATE_INIT -DSBL_SKIP_PINMUX_ENABLE -DSBL_USE_MCU_DOMAIN_ONLY"
endif
diff --git a/packages/ti/boot/sbl/src/ospi/sbl_ospi.c b/packages/ti/boot/sbl/src/ospi/sbl_ospi.c
index 630d37d9..bf52447f 100755
--- a/packages/ti/boot/sbl/src/ospi/sbl_ospi.c
+++ b/packages/ti/boot/sbl/src/ospi/sbl_ospi.c
@@ -93,7 +93,7 @@ bool isXIPEnable = BFALSE;
/* Global variable to check whether OSPI needs to run on 133 MHZ or 166 MHz while booting an application in XIP mode */
uint32_t ospiFrequency;
/* Global variable to check whether OSPI_NAND_BOOT is defined or not */
-bool gIsNandBootEnable = BFALSE;
+bool gIsNandBootEnable = BTRUE;
/* Global variable to check whether combined ROM boot image format is used or not */
extern uint8_t combinedBootmode;
--
2.25.1
Hi,
Could you please explain why you are uncommenting this function and this modification isn't visible in the code snippets you sent me?
I can take some code snippets for you to see.
Can you please tell me why you modified the board_ddrRegInit.h file? Are you using a different DDR or the same DDR?
It will get stuck for a while
Please connect to the CCS and identify the exact api that is causing the code stuck issue.
Regards,
Karthik
sorry for late
Could you please explain why you are uncommenting this function and this modification isn't visible in the code snippets you sent me?
Because this patch is a modification relative to the native SDK, the following comments are the results of debugging. The reason why there are no comments is that there is no effect.
Can you please tell me why you modified the board_ddrRegInit.h file? Are you using a different DDR or the same DDR?
the ddr config file is copy form sdk805,it works fine ,It's different from evm board which is 4GPlease connect to the CCS and identify the exact api that is causing the code stuck issue.
There is no condition to use ccs debugging here for the time being,has another way to debug?
Hi,
There is no condition to use ccs debugging here for the time being,has another way to debug?
I apologise. not able to locate the stuck code without CCS support
Regards,
Karthik
