TMS320C6678: HOW to convert CCS output file *.out into SPI-NORFlash bootable format only use the RBL(without IBL)?

Chuan Xu said:

  I'm looking for a method for  Booting App.bin without IBL, only using the RBL.

Please use this link:- [FAQ] TMS320C6657: How to run the direct SPI-BOOT example on TI-C6657-EVM without IBL ? - Processors forum - Processors - TI E2E support forums

PLEASE NOTE:- USE THIS LINK for the conversion method, you asked for.

The source code given is for C6657 device and not for C6678.

---

The wiki that you have mentioned are de-commissioned long back.

https://www.ti.com/lit/an/spracn2/spracn2.pdf --- Keystone boot loader and resources ----> This is same as that of the wiki, you mentioned above.

Yes, it is true that the "C6678_directROM_boot_examples.zip" link given navigates to some wrong address.

Let me try to find out ( I am not confident enough to get this particular source code as the wikis are no more).

For the time being, you can use the source code of C6657 and modify it for C6678.

Regards

Shankari G

Thanks, is that OK if I'm working under CCSV5.5?

Chuan Xu

For this example, yes, it is ok to use CCS 5.5.

If you use the latest processor SDK 6.3, then you need CCS 9.3

Regards

Shankari G

Thanks.

Since I didn't find C6678's C6678_directROM_boot_examples.zip, I used 0435.C6657_directROM_Boot_example.zip that you provided to me.

But there are some question:

1. The bootEmif4Tbl_s defined in the example is different from RBL(C6678), is that a problem for C6678's RBL to bootloader the example's image?

 The value of "emif4Cfg" in the spiboot.c in C6657's example is not suitable with C6678, did you find the C6678_directROM_boot_examples.zip ？ I think that would be much better.

#pragma  DATA_SECTION (emif4Cfg, ".emif4Cfg")
const BOOT_EMIF4_TBL_T  emif4Cfg =  {

    BOOT_EMIF4_ENABLE_MSW_pllCtl          | \
    BOOT_EMIF4_ENABLE_MSW_sdRamTiming1    | \
    BOOT_EMIF4_ENABLE_MSW_sdRamTiming2    | \
    BOOT_EMIF4_ENABLE_MSW_sdRamTiming3    | \
    BOOT_EMIF4_ENABLE_MSW_ddrPhyCtl1      | \
    BOOT_EMIF4_ENABLE_MSW_sdRamRefreshCtl | \
	BOOT_EMIF4_ENABLE_MSW_sdRamOutImpdedCalCfg | \
	BOOT_EMIF4_ENABLE_MSW_sdRamConfig,

    BOOT_EMIF_ENABLE_SLSW_config0 | \
	BOOT_EMIF_ENABLE_SLSW_config6 | \
	BOOT_EMIF_ENABLE_SLSW_config7 | \
	BOOT_EMIF_ENABLE_SLSW_config8 | \
	BOOT_EMIF_ENABLE_SLSW_config9 | \
	BOOT_EMIF_ENABLE_SLSW_config10 | \
	BOOT_EMIF_ENABLE_SLSW_config18 | \
	BOOT_EMIF_ENABLE_SLSW_config19 | \
	BOOT_EMIF_ENABLE_SLSW_config20 | \
	BOOT_EMIF_ENABLE_SLSW_config22 | \
	BOOT_EMIF_ENABLE_SLSW_config12 | \
	BOOT_EMIF_ENABLE_SLSW_config23 | \
	BOOT_EMIF_ENABLE_SLSW_config21,      /* Config select slsw */
    0,      /* Config select lsw  */
    
    3,      /* pllPrediv  */
    40,     /* pllMult    */
    2,      /* pllPostDiv */

    0x62477AB2,  /* sdRamConfig */
    0,           /* sdRamConfig2, dont care*/
    0x0000144F,  /* sdRamRefreshCtl  */
    0x1333780C,  /* sdRamTiming1 */
    0x30717FE3,  /* sdRamTiming2 */
    0x559F86AF,  /* sdRamTiming3 */

    0,           /* lpDdrNvmTiming, dont care */
    0,           /* powerManageCtl, dont care */
    0,           /* iODFTTestLogic, dont care */
    0,           /* performCountCfg, dont care */
    0,           /* performCountMstRegSel, dont care */
    0,           /* readIdleCtl, dont care */
    0,           /* sysVbusmIntEnSet, dont care */
    0x70074c1f,  /* sdRamOutImpdedCalCfg, dont care */
    0,           /* tempAlterCfg, dont care */

    0x0010010F,  /* ddrPhyCtl1 */

    0,           /* ddrPhyCtl2, dont care */
    0,           /* priClassSvceMap, dont care */
    0,           /* mstId2ClsSvce1Map, dont care */
    0,           /* mstId2ClsSvce2Map, dont care */
    0,           /* eccCtl, dont care */
    0,           /* eccRange1, dont care */
    0,           /* eccRange2, dont care */
    0,           /* rdWrtExcThresh, dont care */

    0x87A0047F, 0, 0, 0, 0, 0, 0x33, 0x3A,
    0x2C, 0x2C, 0x21, 0, 0xAF00002, 0, 0, 0,
    0, 0, 0xB7, 0xB1, 0xA4, 0xA4, 0x98, 0x200,
    0, 0, 0, 0, 0, 0, 0, 0,
    
    0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0,
    0, 0, 0, 0, 0, 0, 0, 0
};

2. The emif4Table defined in  C6678's RBL souce code, which is located to the ".ddr3Table" in C6678_ROM_PG1\main\mainemif4cfg.c， BUT I can't find where is the ".ddr3Table" defined in the RBL, and  what is the dest address of it.

#pragma DATA_SECTION (emif4Table, ".ddr3Table")
#pragma DATA_ALIGN (emif4Table, 4)
BOOT_EMIF4_TBL_T emif4Table;

3. I want to trace the RBL running state, accroding to other''s guide, we can Load Symbols to the device and using HW-Breakpoints to trace it. My Question is : HOW TO COMPILE & Build RBL, and what's the SYMBOLS file? Is there any built SYMBOLS files I can uese?

Thanks Again!

I found the C6678's example here: TMS320C6678: C6678 EVM SPI boot example (without IBL) 的源码 - 处理器论坛 - 处理器 - E2E 设计支持 

Chuan Xu said:

HOW TO COMPILE & Build RBL,

RBL is just for our reference.

( RBL stands for ROM BOOT Loader. It is not meant to be changed by the user/customer. )

It cannot be re-compiled / built.

Regards

Shankari G

If RBL cannot be compiled/built, HOW can I get the SYMBOLS file? I want to trace the RBL running state.

Below is the wiki from 7357.Debugging Boot Issues.zip donwed from TMS320C6678: SPI boot 失败 - 处理器论坛 - 处理器 - E2E 设计支持 (ti.com)

Chuan Xu,

Download the ROM BOOT Source from here.

https://software-dl.ti.com/sdoemb/sdoemb_public_sw/rbl/1_0_C6678/index_FDS.html

--

The picture is for the IBL ( Intermediate boot loader )  or the secondary boot loader which the user uses to load into the EEPROM or the NOR/NAND.

This picture is not for the RBL.

--

For more info on IBL, refer this FAQ:-

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1073147/faq-tms320c6678-how-to-flash-the-ibl-intermediate-boot-loader-into-eeprom-and-how-to-flash-the-application-binary-into-nor-how-to-boot-the-ibl-application-binary

--

Regards

Shankari G

Thanks a lot.

Now I can trace the RBL only through the internal registers  and the records in L2SRAM according to the Data Sheet's Chapter "2.4 Bootloader section in L2 SRAM" .

Then I followed the  C6678_directROM_boot_examples.zip  guide, rebuilt the led_play project and used the spi_boot.bat to create the app.dat, and wrote to the SPI-NOR Flash. But After POR, it still not works.

From the "Boot log"(0x00873200) and RBL source code, I found that RBL is running in the loop of "bootMainSpi".

The BOOT log register info is below:

 From the "Boot log" info, there are 10 log records in such format:

typedef struct bootLogEntry_s  {

    void    *fileName;     /* Pointer to a string containing the name of the file which is logging */
    UINT32   line;         /* The log line number */
    SINT32   logCode;      /* The log code */
    
} bootLogEntry_t;

So, I thought maybe image format is not right, and I tried to check out if the file format is wrong, BUT I didn't find any docs about the FILE FORMAT created by the cl6x/Hex6x/b2i2c/b2ccs/romparse... tools. 

There seems to be none descriptions of the FILE FORMAT in sprui03b-Assembly Language Tools-v8.2.x.pdf. 

I found it in sprab89a-Embedded Application Binary Interface.pdf

Hi, I've checked the format of led_play.out built by the source code from C6678_directROM_boot_examples.zip , That's right.

Then, according to the C6678_SPIboot_usersManual.pdf , after compiling , we have to run C6678\spiboot\build\spiboot.bat.

In the spiboot\build\spiboot.bat， there several steps：

1. Section 1:  Hex6x, used to convert the *.out to Boot Table format object: *.btbl;
2. Section 2:  b2i2c, Convert to i2c/SPI format： *.btbl.i2c;
3. Section 3: b2ccs, Convert to CCS downloaded format;
4. Section 4: romparse,  Adding Boot parameter Table;
5. Section 5: byteswapccs , swaps the bytes for big endian RBL;

I do understand the Section 1,2,4,5. 

But I don't understand the meaning of Section3: b2ccs. My quesions:

1. Why the i2c formatted file(*.btbl.i2c) need to be converted into CCS acceptable .dat format using b2ccs? 
2. Dose Section 4 must operation after Section3?
3. Is that OK to add Boot Parmeter Table to the SPI format object(*.btbl.i2c) directly?

By the way, since there is NO I2C-EERPROM on my borad, I'm not using the writer\nor\evmc66xxl\bin tools to burn the finnal app.dat into the SPI NORFlash, I wrote a single SPI-writer project to do the job instead. Here is what the project doing:

1. Use fopen()/fread()  to read the file content in to MSM(0x0c300000);
2. Init the SPI, and write the file content from MSM(0x0c300000) to the SPI-NOR Flash(offset:0x00);
3. Read the wrote content from the flash and check.

Q1: Is that OK?

Q2: From the C:\ti\pdk_C6678_1_1_2_6\packages\ti\platform\evmc6678l\platform_lib\src , I found the default SPI NorFlash in  only support PLATFORM_DEVID_NORN25Q128,  But I'm using the other chips, My question is : Dose RBL support the other type of chips?

Chuan Xu

Chuan Xu said:

By the way, since there is NO I2C-EERPROM on my borad, I'm not using the writer\nor\evmc66xxl\bin tools to burn the finnal app.dat into the SPI NORFlash, I wrote a single SPI-writer project to do the job instead. Here is what the project doing:

1. Use fopen()/fread()  to read the file content in to MSM(0x0c300000);
2. Init the SPI, and write the file content from MSM(0x0c300000) to the SPI-NOR Flash(offset:0x00);
3. Read the wrote content from the flash and check.

Q1: Is that OK?

Yes. It is OK.

Chuan Xu said:

Q2: From the C:\ti\pdk_C6678_1_1_2_6\packages\ti\platform\evmc6678l\platform_lib\src , I found the default SPI NorFlash in  only support PLATFORM_DEVID_NORN25Q128,  But I'm using the other chips, My question is : Dose RBL support the other type of chips?

Yes, the RBL support other chips too.

( RBL does the initialization of all interfaces. The peripheral driver will reside in the software layer above the RBL. So, By default, it should support all the compatible NOR chip devices....) 

The platform support library has an example to support the NORN25Q128 device. The user can modify the platform library source file to include their NOR devices.

This platform library is meant for customer's usage. It can be compiled and rebuilt.

To re-build the platform library, please follow the steps given here:-

=====================================================

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1071286/faq-tms320c6678-how-to-build-and-run-the-platform-test-on-c6678-evm

[FAQ] TMS320C6657: How to solve the CSL errors in the Platform test example of PDK in processor SDK 6.3 ? - Processors forum - Processors - TI E2E support forums

[FAQ] TMS320C6657: How to solve the Cerrno Error in the Platform test example of PDK in processor SDK 6.3 ? - Processors forum - Processors - TI E2E support forums

Regards

Shankari G 

Thanks a lot.

Now, I can boot my led_play project object file following the 0647.C6678_directROM_boot_examples.zip . Ofcourse, I did some effords:

nysh.spi.map:  After changing the value of "sw_pll_prediv", "sw_pll_mult", It worked on the customs board, and our LEDS drives OK.

section {
 boot_mode = 50
 param_index = 0
 options = 1
 core_freq_mhz = 1000
 exe_file = "led_play.i2c.ccs"
 next_dev_addr_ext = 0x0
 sw_pll_prediv = 0
- sw_pll_prediv = 5
- sw_pll_mult = 32
+ sw_pll_prediv = 0
+ sw_pll_mult = 19
 sw_pll_flags = 1
 addr_width = 24
 n_pins = 4
 csel = 0
 mode = 0
 c2t_delay = 0
 bus_freq_mhz = 0
 bus_freq_khz = 500
}

BUT, There comes with a New question. Since  there is no I2C-EEPROM on our custom board, and our app's sections are too much and big, so we have to put some of them into DDR. So we have to INIT DDR3 before bootloader move them into DDR memory.

I think there are 3 methods to deal with it.

1. Add a emif4Cfg table in my app codes to decide which registers to be set/clear in the RBL process.(After I read the RBL src code, I think it's a way to do it, and it did work!)
2. Add a Boot Config Table in the app.dat before writing it into the SPI-NOR Flash;
3. Add a boot.asm, and use it as a second-bootloader to boot our app object;

There are some questions about each method:

Q1 about method 1:

After POR, I found the configs are configured to the dest-registers, but the DDR is still not stable. Then I found the main PLL registers value are not the same as  them afater the GEL files excuted. How to set the main PLL with the .emif4Cfg table?  Whether the following params works or not?

    0,      /* pllPrediv  */
    7,      /* pllMult    */
    0,      /* pllPostDiv */

In C6678's Data Sheet, there is way to calc the CLK: CLK = CLKIN × ((PLLM+1) ÷ ((OUTPUT_DIVIDE+1) × (PLLD+1)))

PLLM-->pllMult?

PLLD-->pllPostDiv?

OUTPUT_DIVIDE-->?

CLKIN-->? (Our custom board is 100MHz, but how could RBL get this value?)

Q2 about method 2:

How create a Boot Config Table and add it into the burning object files? 

Q3 about method 3:

Since our app object file is wrote into the SPI-flash， so we have to boot it from SPI-NOR FLASH, Is there any demo in assembl file?

Regards

Chuan Xu

Chuan Xu

I guess, your first original question has been resolved.

Appending more questions on a single post is not recommended.

Please open up a new post with this one.

--

As you know, a new post will get more attention than appending different questions on the same.

Regards

Shankari G