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Tool/software:
Dear support：
Our customers need to consult some questions when using 6678 SRIO, and hope to help answer them. The questions are as follows
the chip used is 6678.
The phenomenon is that in the process of ddr operation on ddr or edma, if the srio writes the drr (using streaming write), the srio dies.
This article mentions that priority doesn't help, I also think so, and also mentions that two corepacs can't access the same DDR3 memory at the same time, I think that although they can't access at the same time, but when DSP cores and EDMA access DDR, they can feel the quorum mechanism, but SRIO can't, SRIO joins and dies if there is a bus conflict, so it can't solve my problem.
This article is the same as I thought, the problem will not be caused by bandwidth, but there is no solution.
This one is the same as my question, and the TI engineers are thinking about DDR, and I don't think there's anything wrong with that. But the reply is the original text in the manual, he mentioned the priority of srio, I think like this, setting the priority of the device does not seem to have any effect in srio, so I distinguish the service category in the ddr, srio all the way, edma all the way, but I can't find the priority of the service class.
I hope engineers can intervene to help solve the problem. Thank you very much and look forward to you.
Personal thoughts: Srio's death problem is not like a problem on the DSP's side, I feel more like a problem on the FPGA side, FPGA died after the president, but his priority is the highest, and he shouldn't be the president However, whether it is the program that lacks a mechanism, but I am not an FPGA engineer, and I can't make a detailed judgment.
I hope your engineers will step in instead of sending links, thank you very much for looking forward to it.
