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TDA4VM-Q1: enable mcu_spi0 in r5 spl

xiuqi huang
Prodigy 150 points
Part Number: TDA4VM-Q1

Tool/software:

Hi, team

We want to use mcu_spi0 in r5 spl,  we add mcu_spi0 in dts of r5 spl

we use spi_get_bus_and_cs to get the spi, but error occurred

It seems like there is no 274 in soc_dev_list in arch/arm/mach-k3/j721e/dev-data.c，how can we add a new dev?

The default driver of pds(power-domains) is ti-power-domain.c, if we change it to ti-sci-power-domain.c, The board will get stuck during the r5 spl stage

  • 0
    TI__Mastermind 34170 points

    Hi,

    What's is the SDK version being used here?

    Regards,

    Tanmay

  • 0
    Prodigy 150 points

    The SDK version is 0902, but we have not updated u-boot on our own project, the baseline for u-boot code is 08.00.00.004

  • 0 in reply to xiuqi huang
    TI__Mastermind 34170 points

    Hi,

    In the "soc_dev_list" in "arch/arm/mach-k3/j721e/dev-data.c", you can add a line "PSC_DEV(274, &soc_lpsc_list[0])," to add 274 to the devices to power on.

    xiuqi huang said:
    The default driver of pds(power-domains) is ti-power-domain.c, if we change it to ti-sci-power-domain.c, The board will get stuck during the r5 spl stage

    ti-sci-power-domain.c won't work at this time as dm binary is not running yet which runs the sciserver.

    Regards,
    Tanmay

  • 0 in reply to Tanmay Patil
    Prodigy 150 points

    Hi，

    I add PSC_DEV(274, &soc_lpsc_list[0]) in the "soc_dev_list" in "arch/arm/mach-k3/j721e/dev-data.c"， and it worked. 

    In U-boot stage, I can set the speed of spi by function  _omap3_spi_set_speed()

    I set the priv->freq to 2000000, and it's actual speed I measured by Digital Logic Analyz is also 2Mhz.

    But with same code in r5 spl stage, the actual speed is 12.5Mhz.

    How can I set spi to 2Mhz in r5 spl

  • 0 in reply to Tanmay Patil
    Prodigy 150 points

    Hi, 

    How can I add k3_clks 274 for mcu_spi0 in "arch/arm/mach-k3/j721e/clk-data.c"

    ...

  • 0 in reply to xiuqi huang
    Prodigy 150 points

    Correct the description of this issue：the actual test result in U-boot is 1.56MHz. In r5 spl, I can set the speed to 1.56MHz by setting the div to 0x8. But there is another issue, when rebooting, the SPI speed tested during the r5 spl phase was 190kHz

  • 0 in reply to xiuqi huang
    TI__Guru**** 452285 points

    , any further update on this thread? 

  • 0 in reply to xiuqi huang
    TI__Expert 7091 points
    xiuqi huang said:
    Correct the description of this issue：the actual test result in U-boot is 1.56MHz. In r5 spl, I can set the speed to 1.56MHz by setting the div to 0x8. But there is another issue, when rebooting, the SPI speed tested during the r5 spl phase was 190kHz

    Hi Xiuqi

        is this issue fixed now?

    Regards

       Semon