AM6442: Unable to operate RMII in 100M mode

Hi team,

This question is a related issue. Because the original issue has been locked in. The specific situation is the original problem.
In the original question, forwarded to the English forum: e2e.ti.com/.../am6442-configure-ent1-port-to-100mbps I have checked.
Here is a supplementary explanation:

① The RMII interface output of the AM6442 CPSW module is a 10M baud rate, not converted to 10M baud rate through PHY.
② RMII_REF_CK is a 50MHz clock provided by an external clock source, not 5MHz.
The pins I measured are shown in the diagram below. I urgently hope to solve the problem that the RMII interface of the AM6442 CPSW module cannot output 100M baud rate timing, instead of extending the issue to the configuration of the PHY (I only output RMII and test it directly on the MCU pin; I think this is unrelated to the PHY)

I hope TI engineers can pay attention to the relevant fields of the register CPSW-PN_MAC-CONC-REG_k as follows: perhaps it can be helpful.

Hi Jiahui Gao,

Thanks for your query and patience.

I will check on this and get back to you.

Regards

Ashwani

Hi Ashwani，

Any updates？

Hi Ashwani，

Any updates？

Hi Jiahui Gao,

I was on vacation. So could not check on this.

Will get back to you by next week.

Regards

Ashwani

Meanwhile, you can refer below related discussion

(+) MCU-PLUS-SDK-AM243X: CPSW RMII mode unavailable for AM234x (only RGMII) - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

You are working on custom board or AM64-EVM itself ?

Regards

Ashwani

Hi

1. The board is custom-made and uses the AM6442; The RMII pin combination used is mentioned in the post above.

2. The development of CPSW RGMII has been completed in TI AM64X-EVM board.

Almost all CPSW related drivers are developed using registers-based methods, which have been thoroughly tested and verified. This is sufficient to indicate that independent register development has the capability to do so. Then in the customized board, I will modify the corresponding register configuration to RMII mode. I found that there are few descriptions about RMII registers, and even errors (as mentioned in the previous post).

3. Due to confidentiality concerns, I am unable to provide you with register configurations. But I believe that TRM's RMII related register description for CPSW is missing or incorrect. For example, the register 0x08022330 mentioned in the previous post.

I hope you can read the above post thoroughly and answer the corresponding questions.

4. I have confirmed that the port selected is the RMII interface through the following methods.

SOC_controlModuleUnlockMMR(SOC_DOMAIN_ID_MAIN, 1); 
*(vuint32_t*)(0x43004044) = 1; //cpsw0-port1 2选择RGMII 1选择RMII
 *(vuint32_t*)(0x43004048) = 1; //cpsw0-port2 2选择RGMII 1选择RMII
SOC_controlModuleLockMMR(SOC_DOMAIN_ID_MAIN, 1);

5. In SDK C: In the \ ti \ mcu_plus_stk_am64x_09_02/00_50 \ examples \ networking \ enet_layer_2cpsw routine, I tried to modify this example to the RMII interface, but unfortunately, it doesn't even work in 10M mode.

Has TI fully validated the RMII interface? Can you provide the RMII interface routine for CPSW. If possible, I think I should be able to independently solve the problem of RMII only working at 10M and unable to communicate at 100M.

Jiahui Gao said:

The board is custom-made and uses the AM6442; The RMII pin combination used is mentioned in the post above.

I would like to suggest you to get your schematic reviewed by TI-HW team to avoid any HW issues ?

Jiahui Gao said:

Has TI fully validated the RMII interface?

Our test setup tests only CPSW-RGMII mode for every release.

Jiahui Gao said:

In SDK C: In the \ ti \ mcu_plus_stk_am64x_09_02/00_50 \ examples \ networking \ enet_layer_2cpsw routine, I tried to modify this example to the RMII interface, but unfortunately, it doesn't even work in 10M mode.

Did you also try with latest release and confirm tthe issue as it will be faster for me to reproduce the issue on latest baseline?

Jiahui Gao said:

Due to confidentiality concerns, I am unable to provide you with register configurations. But I believe that TRM's RMII related register description for CPSW is missing or incorrect. For example, the register 0x08022330 mentioned in the previous post.

Can you ask TI filed team (FAE) (if you are in contact with someone) to start an e-mail regarding this ?

Regards

Ashwani

Jiahui Gao said:

but unfortunately, it doesn't even work in 10M mode.

Are you sure PHY is configured correctly?

Regards

Ashwani

Hi Ashwani，

Could you please report the issue of missing RMII register descriptions to the relevant engineers at TRM? (Specific omissions and errors were mentioned in my post)

1. We will do a hardware design check with FAE.

2. The demo is not the latest, but the SDK version can be seen from the file index, which is sufficiently new. Starting from self-development of AM6442, we have downloaded no less than 4 SDK versions from TI official website. I just checked the latest SDK release notes and RMII has not conducted testing and verification, so I do not want to continue updating the SDK version for testing.

3. It is normal to use the same circuit and software configuration of PHY in other projects.
Secondly, from the RMII-TD0 RMII-TD1 RMII-TEN signal of AM6442, the waveform was captured by an oscilloscope and displayed as operating at a frequency of 10M. I am unable to make it operate at 100M
Finally, I attempted to configure the PHY to 10M mode, and the data transmission and reception were correct and error free. This indicates that there should not be too many errors in my configuration of CPSW RMII.
The only question is why the PHY is configured to 100M mode, and why isn't the RMII interface mode of CPSW automatically adjusted to 100M? Since automatic adjustment is not possible, why not provide register configuration for modifying RMII interface timing? I think this should be sufficient to indicate that the source of the 10M issue is not from the PHY configuration.

4.In the customized board, RMII_CLK is provided with 50M timing by PHY to the RMII_REF_CLK pin of AM6442. In the TRM description, a 50MHz clock input may indeed enable RMII to operate at 10Mbps As shown in the following figure

I have confirmed to configure the PHY to 100M. This issue can also be verified through a PC computer. As shown in the following figure:

I am certain that the PHY inside the customized board will work in 100M mode in consultation with the PC computer, however, the timing output of AM6442 RMII_EN RMII_TD0 RMII_TD1 is in 10M mode. This is very unreasonable.
I conducted a test: disabling the 100M capability of the PHY and retaining only 10M capability; The rest of the code remains completely unchanged. The timing output of AM6442 RMII_EN RMII_TD0 RMII_TD1 is still in 10M mode. As shown in the figure below: 

The PC captures network packets, which are consistent with the data written.

If your company has not conducted any interface testing on CPSW RMII in the AM6442 series, please kindly conduct the corresponding testing. This is very important to me. I strongly suspect that AM6442 CPSW RMII only supports 10M mode.

If there are corresponding tests indicating that AM6442 CPSW RMII supports 100M mode, please update to the SDK package as soon as possible or publish a separate sample.

?? ? said:

AM6442 RMII_EN RMII_TD0 RMII_TD1 is in 10M mode. This is very unreasonable.

PHY is in master mode. correct ?

Here is one related thread to refer.

(99+) AM2432: network failure for am2432 with phy dp83822 - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

Regards

Ashwani

PHY is in master mode, and the specific situation is as follows.

The PHY pin connections used in the customized board are shown in the following figure:

As shown in the above figure, the PHY uses LAN8720A. The REF_CLK connection between CPSW MAC (RMII) and LAN8720A is shown in the following figure:

I have reviewed the post you shared. But it doesn't seem to have helped.

?? ? said:

I strongly suspect that AM6442 CPSW RMII only supports 10M mode.

This is not the case, we have customers working with CPSW-RMII mode on AM64x/AM243x.

?? ? said:

If there are corresponding tests indicating that AM6442 CPSW RMII supports 100M mode

I agree, this is a gap in our test coverage. I have fraise this to concern team with tracking no: SITSW-5832.

Can you check proper pin muxing is generated for RMII from sysconfig ?

Regards

Ashwani

Hello, I have borrowed the relevant configuration of SYSCFG RMII for pin reuse, as shown in the following figure.

I think the core of solving the problem may be the XGIG field of the CPSW-PN_MAC-CONC-REG_k register. According to the field, the rate is determined by pn_xgig. But I couldn't find any relevant description when searching TRM.