[FAQ] AM62A7 / AM62A7-Q1 / AM62A3 / AM62A3-Q1 Design Recommendations / Custom board hardware design – common queries for PMIC TPS6593

Kallikuppa Sreenivasa

Guru**** 165379 points

Part Number: AM62A74
Other Parts Discussed in Thread: TPS6594-Q1, TPS65224

Tool/software:

HI Board designers,

I am designing my board using TPS6593 PMIC

Are there some common recommendation or observations that i should be aware?

3 months ago

0 Kallikuppa Sreenivasa 3 months ago

TI__Guru**** 165379 points

HI Board designers,

Refer below, FAQs, common queries and replies

[FAQ] List of FAQs for TPS6594-Q1, TPS6593-Q1, LP8764-Q1 PMICs

https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1372241/faq-list-of-faqs-for-tps6594-q1-tps6593-q1-lp8764-q1-pmics?tisearch=e2e-sitesearch&keymatch=tps6593#

AM62A7: Changing the VDD_CORE voltage

If you are using the SK-AM62A-LP EVM with the TPS65931211-Q1 PMIC, then you can modify the hardware to change the default voltage on VDD_CORE which is supplied by the PMIC multi-phase Buck1/2/3.

The GPIO6 of the PMIC was configured to set the voltage on Buck1/2/3 with the following polarity:

High: Buck1/2/3 = 0.85V
Low: Buck1/2/3 = 0.75V

During power up, the PFSM for the '1211 reads the state of GPIO6 10ms after it has enabled the 3.3V load switch. If GPIO6 is pulled up to that signal, BUCK123 will be 0.85V.

Therefore, from the PMIC perspective Pull GPIO6 HIGH to the 3.3V load switch signal

This information along with all the PMIC NVM configuration was documented in the following user's guide: https://www.ti.com/lit/pdf/slvucm3

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 1 month ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 165379 points

HI Board designers,

Refer below, FAQ

[FAQ] TPS6594-Q1: Residual Voltage Check

https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1103444/faq-tps6594-q1-residual-voltage-check

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 11 days ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 165379 points

HI Board designers,

Using TPS65224 for AM62A

Refer below, FAQ

e2e.ti.com/.../5594165

(38) [FAQ] AM62P / AM62P-Q1 Design Recommendations / Custom board hardware design – common queries for PMIC TPS65224-Q1 - Processors forum - Processors - TI E2E support forums

Additional inputs

We get request from schematic review team to add a buffer between PMIC TPS65224 RSTOUT pin and SOC MCU_PORZ pin.
I think the reason is that the SOC MCU_PORZ will require the rising edge and falling edge. So would you like to share the detail.
Such as the rising edge slew rate, rising time and so on required by MCU_PORZ as input?

The PMIC nRSTOUT is a open drain slow ramp output from the PMIC.

When a slow ramp reset input is applies to the MCU_PORz there are likely chances that the internal reset circuit could glitch.

A discrete push pull output buffer is recommended to minimze the slew.

We do not have a spec for the MCU_PORz. The recommendation is faster the better. (<10ns)

if possible, could you help me confirm the timing relationship for Buck1 (VDD_CORE) and LDO0 (VDDR_CORE)

In the startup sequence the buck1 goes high at 5.9 ms and LDO3 (VDDR_CORE) at 6.45 ms. In the shutdown LDO3 goes down at 0.5 ms and buck 1 at 1 ms. Timings are measured from the enable rising/falling edge.

Partial IO - What about VDD_CANUART (core supply)?

For Partial IO, VDDSHV_CANUART (1.8V/3.3V) and VDD_CANUART (0.75V/0.85V) are both connected to always-ON rails. When Partial IO mode is not use, the CANUART supplies are connected to the same rails as the remaining IOs and CORE.

Regards,

Sreenivasa