AM68A: J721S2 ( AM68A & TDA4) PCIe PTM

Part Number: AM68A
Other Parts Discussed in Thread: AM68

Tool/software:

Dear Team,

-> Is it possible that you share the TI programing model of PTM ( PCIe)  and J7 implementation mentioned by Jian in the e2e thread ?
-> Also can you tell if the output from the red marked block can be connected to the HW2_TS_OUS or needs to be connected to HW1_TS_PUSH?
->Does the PCIE Subsystem use the Main Domain CPTS0 or does it have a dedicated PCIe CPTS?
Best Regards,
d.
  • Hi D.,

    Reposting my email response:

    "as for the PCIe PTM thread, unfortunately Jian is no longer an active employee at TI, so it will be hard to find the exact documentation that Jian is referring to in the 4 year old forum thread. Additionally, there is no PCIe PTM software implementation planned for the AM68 devices.

    The most recent related activity that I could find is this FAQ for AM64 using RTOS: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1409291/faq-processor-sdk-am64x-how-to-enable-rtos-based-pcie-ptm/5396014#5396014. But as a warning, there are no RTOS based PCIe driver for the AM68 devices, and the RTOS code base used for AM68 and AM64 are slightly different, so the portability of this FAQ to AM68 is questionable. However, the PCIe controller IP on the SoC are the same, so the Linux driver is the same, so the example can be referenced somewhat (aka, what registers are important, and the flow)."

    -> Also can you tell if the output from the red marked block can be connected to the HW2_TS_OUS or needs to be connected to HW1_TS_PUSH?

    Looks to be only connected via HW1_TS_PUSH to CPTS inside PCIe subsystem and CPTS_HW1_PUSH is the signal going out of PCIe subsystem directly from that mux.

    ->Does the PCIE Subsystem use the Main Domain CPTS0 or does it have a dedicated PCIe CPTS?

    There is a CPTS module inside the PCIe subsystem:

    Regards,

    Takuma