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DRA829V: [EP2000] CPSW-9G Port 7 Data is not routing to Main21

Part Number: DRA829V

Tool/software:

Hi TI Team,

We are using PSDK7.3

Below is the our SW architecture, Where data from External switch (port 7) is copied to Port 7 of internal Switch.

Usecase:

Ingress Port mirroring is enabled in external switch for ports 1 and 2, 
Ingress monitoring destination port is PORT 7 of external switch.

CPSW9G Port 7 will receive the data and pass to Main2_1 core.

Port1 is sending ARP request (broadcast) on network.
Port7 and Port 2 will receive the data.

Port7 successfully forwarding this request to Main2_1.
Port2 replied with unicast packet, This will go to Port1 and also Port 7( because of port mirroring feature).



Issue: 
CPSW-9G is not passing this unicast packet to Main2_1.

We verified the statistics in CPSW-9G, it confirms it received it, but not Main2_1.

In Main2_1, we have the ISR function where we are incrementing the counter for each frame.
it confirms only broadcast received and not unicast.

Please help us to debug further.

We can have sort sync to understand issue better.

Thanks,
Venu H

  • Hi,

    Port mirroring will egress the packet from destination mirrored port.

    Ingress Port mirroring is enabled in external switch for ports 1 and 2, 
    Ingress monitoring destination port is PORT 7 of external switch.

    Here, packets ingress from Port-1, Port-2 are egresses from Port-7.
    Please refer to FAQ for more details.
    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1283294/faq-tda4vm-how-do-i-configure-enable-port-mirroring-in-cpswng

    Also, Uni-cast packet will be forwarded to single Port as ALE has Port number not a Port Mask. So, packets can only send to one Port from ALE.
    If Uni-cast MAC is intended for Host Port then only Host Port will receive.

    Best Regards,
    Sudheer

  • Hi Sudheer,

            OK if unknown Unicast packet are received on PORT-7 of internal switch, we need to forward those on MAIN2_1 core, so how can we do this ? can we have short synch up on this topic?

    Regards,

    Venu. 

  • Hi,

    OK if unknown Unicast packet are received on PORT-7 of internal switch, we need to forward those on MAIN2_1 core, so how can we do this ? can we have short synch up on this topic?

    Un-known packets are dropped by default and not forwarded to Host Port.
    As those are not forwarded to Host Port we can't route those to MCU2_1. In order to route to MCU2_1 we need to classify the packet then only we can able to route to MCU2_1.

    Best Regards,
    Sudheer

  • Hi Sudheer,

    As you know our product is Data logger, we should receive every frame.
    Can you please check is there a way to achieve this ?

    Un-known packets are dropped by default and not forwarded to Host Port.

    By default you are dropping, but Is there a possibility to remove this default configuration ? 

    Thanks,
    Venu H

  • Hi,

    Un-known packets are dropped by default and not forwarded to Host Port.

    By default you are dropping, but Is there a possibility to remove this default configuration ? 

    We can flood unknown unicast packets to Host Port.
    But, it is not recommended as if we enable, all unknow unicast packets will be forwarded to Host Port.

    Best Regards,
    Sudheer

  • Hi Sudheer,

    We can flood unknown unicast packets to Host Port.
    But, it is not recommended as if we enable, all unknow unicast packets will be forwarded to Host Port.

    May i know where to enable this ?
    We will just check whether it will meet our requirements or not.

    Thanks,
    Venu H

  • Hi,

    We can flood unknown unicast packets to Host Port.
    But, it is not recommended as if we enable, all unknow unicast packets will be forwarded to Host Port.

    May i know where to enable this ?
    We will just check whether it will meet our requirements or not.

    You can try by enabling EN_HOST_UNI_FLOOD from CPSW ALE Control register.


    Best Regards,
    Sudheer

  • Hi Sudheer,

    Please help us from SW side.

    We need exact function name and where to call it.

    Thanks,
    Venu H

  • MOM of today's meeting : (09/12)

    1) ALE CTRL register update @Aptiv
    2) if point 1 didn't work, Include the patch shared, to capture the datas and test @Aptiv

    Based on these above, if needed we will have another follow up discussion

  • Hi,

    Thanks for capturing the Minutes.

    Please share the captured ALE & Policers data before and after test in E2E, if you are still facing the issue.

    Best Regards,
    Sudheer

  • Hi Sudheer,

    Point 1 didn't work, 
    Will update the patch and share the data ASAP.

    Thanks,
    Venu H

  • Hi Sudheer,

            Could you please attach the patch file for CPSW debugging ?

    Regards,

    Venu.

  • Hi Sudheer,

    Patch you given above for collecting the statistics is not working in 7.3 PSDK.
    its failing in Enet_ioctl().
    Please reply with your available time to discuss on this.

    Thanks,
    Venu H 

  • Hi,

    its failing in Enet_ioctl().
    Please reply with your available time to discuss on this.

    Task for statistics collection to be created after enet_init if we invoke before enet_icotl will fail as we not have enet handler.
    The patch is based on SDK 8.6.

    We have created task at the ends of "EthApp_initEthFw" API.

    Best Regards,
    Sudheer

  • Hi Sudheer,

    Same way only we created task in 7.3 as well,

    We need live debugging !!
    Can i schedule call for 3.30PM IST ?

    Thanks,
    Venu H

  • Hi,

    Can i schedule call for 3.30PM IST ?

    Please schedule a call from 4PM to 4.30 PM.

    Best Regards,
    Sudheer

  • Hi All,

    Update from todays (10-Dec-2024) debug call.

    TI will provide FAQs for configuring the ALE & Policers for remote clients.
    TI will share details of CPSW registers to check for Default Ports VLAN.
    Aptiv need to try using this and create an ALE & Policer entry for Port-7 VLAN and forward to MCU2_1.


    FAQ for ALE & Policer configuration for remote client (A72 (MPU1_0), instead of MPU1_0 you need to use for MCU2_1.
    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1011237/faq-tda4vm-how-to-configure-cpsw-5g-9g-ale

    CPSW register details for Port VLAN. Below k range from 0 to 7 corresponding to Port-1 to Port-7.


    For ALE dump I have shared a patch to dump ALE & Policers and Statistics.

    Best Regards,
    Sudheer

  • Hi Sudheer,

    We added VLAN configuration as below,

    static int32_t EthApp_addMcu21StaticCfg(Enet_Handle hEnet,
    uint32_t coreId,
    uint32_t flowId)
    {
    CpswAle_SetPolicerEntryInArgs polInArgs;
    CpswAle_SetPolicerEntryOutArgs polOutArgs;
    Enet_IoctlPrms prms;
    int32_t status;

    CpswAle_VlanEntryInfo inArgs;
    uint32_t outArgs;

    /* Add VLAN entry */
    memset(&inArgs, 0U, sizeof (CpswAle_VlanEntryInfo));
    inArgs.vlanIdInfo.vlanId = 100;
    inArgs.vlanIdInfo.tagType = ENET_VLAN_TAG_TYPE_INNER;
    inArgs.vlanMemberList = (1 << CPSW_ALE_MACPORT_TO_ALEPORT(ENET_MAC_PORT_7)) | CPSW_ALE_HOST_PORT_MASK;
    inArgs.unregMcastFloodMask = (1 << CPSW_ALE_MACPORT_TO_ALEPORT(ENET_MAC_PORT_7)) | CPSW_ALE_HOST_PORT_MASK;
    inArgs.regMcastFloodMask = (1 << CPSW_ALE_MACPORT_TO_ALEPORT(ENET_MAC_PORT_7)) | CPSW_ALE_HOST_PORT_MASK;
    inArgs.forceUntaggedEgressMask = 0x1ff;
    inArgs.noLearnMask = 0U;
    inArgs.vidIngressCheck = true;
    inArgs.limitIPNxtHdr = false;
    inArgs.disallowIPFrag = false;

    ENET_IOCTL_SET_INOUT_ARGS(&prms, &inArgs, &outArgs);

    status = Enet_ioctl(hEnet, gEthAppObj.coreId, CPSW_ALE_IOCTL_ADD_VLAN, &prms);
    if (status != ENET_SOK)
    {
    appLogPrintf("%s() failed ADD_VLAN ioctl failed: %d\n", __func__, status);
    }

    polInArgs.policerMatch.policerMatchEnMask = 0U;

    /* Add policer entry for port 7 match */
    polInArgs.policerMatch.policerMatchEnMask = CPSW_ALE_POLICER_MATCH_PORT;
    polInArgs.policerMatch.portNum = CPSW_ALE_MACPORT_TO_ALEPORT(ENET_MAC_PORT_7);
    polInArgs.policerMatch.portIsTrunk = false;

    polInArgs.threadIdEn = true;
    polInArgs.threadId = flowId;
    polInArgs.peakRateInBitsPerSec = 0U;
    polInArgs.commitRateInBitsPerSec = 0U;

    ENET_IOCTL_SET_INOUT_ARGS(&prms, &polInArgs, &polOutArgs);

    status = Enet_ioctl(hEnet, gEthAppObj.coreId, CPSW_ALE_IOCTL_SET_POLICER, &prms);
    if (status != ENET_SOK)
    {
    appLogPrintf("Failed to register PORT 7 policer: %d\n", status);
    }
    if (status == ENET_SOK)
    {
    ENET_IOCTL_SET_NO_ARGS(&prms);
    status = Enet_ioctl(hEnet, gEthAppObj.coreId, CPSW_ALE_IOCTL_DUMP_TABLE, &prms);
    ENET_IOCTL_SET_NO_ARGS(&prms);
    status = Enet_ioctl(hEnet, gEthAppObj.coreId, CPSW_ALE_IOCTL_DUMP_POLICER_ENTRIES, &prms);
    }

    return status;
    }

    We can see corresponding VLAN entry in ALE dump.
    But still the issue is same, any other things we have to taken care ?



    Thanks,
    Venu H

  • Hi,

    Let me check above and provide you feedback? 

    Best Regards, 

    Sudheer

  • Hi,

    We can see corresponding VLAN entry in ALE dump.
    But still the issue is same, any other things we have to taken care ?

    ALE and Classifier are fine, Along with these you need to make following changes.
    1. You need update Port-7's VLAN address as 100.
    2. Also, you need to enable, flood un-known unicast to Host Port.

    Please refer to below ALE lookup process for un-known uni-cast packets.


    Best Regards,
    Sudheer

  • Hi Sudheer,

        We will check above update, but we changed the code to allow all Rx all for MCU2_1 then looks like working fine for now. please check and correct us if any modification or fine tune required and we tested this any frame VLAN or Non VLAN or any random frames getting received in MCU2_1. 

    static int32_t EthApp_addMcu21StaticCfg(Enet_Handle hEnet,
    uint32_t coreId,
    uint32_t flowId)
    {
    CpswAle_SetPolicerEntryInArgs polInArgs;
    CpswAle_SetPolicerEntryOutArgs polOutArgs;
    Enet_IoctlPrms prms;
    int32_t status;

    CpswAle_RxFilter setRxFilter;

    #if 0
    CpswAle_VlanEntryInfo inArgs;
    uint32_t outArgs;

    /* Add VLAN entry */
    memset(&inArgs, 0U, sizeof (CpswAle_VlanEntryInfo));
    inArgs.vlanIdInfo.vlanId = 100;
    inArgs.vlanIdInfo.tagType = ENET_VLAN_TAG_TYPE_INNER;
    inArgs.vlanMemberList = (1 << CPSW_ALE_MACPORT_TO_ALEPORT(ENET_MAC_PORT_7)) | CPSW_ALE_HOST_PORT_MASK;
    inArgs.unregMcastFloodMask = (1 << CPSW_ALE_MACPORT_TO_ALEPORT(ENET_MAC_PORT_7)) | CPSW_ALE_HOST_PORT_MASK;
    inArgs.regMcastFloodMask = (1 << CPSW_ALE_MACPORT_TO_ALEPORT(ENET_MAC_PORT_7)) | CPSW_ALE_HOST_PORT_MASK;
    inArgs.forceUntaggedEgressMask = 0x1ff;
    inArgs.noLearnMask = 0U;
    inArgs.vidIngressCheck = true;
    inArgs.limitIPNxtHdr = false;
    inArgs.disallowIPFrag = false;

    ENET_IOCTL_SET_INOUT_ARGS(&prms, &inArgs, &outArgs);

    status = Enet_ioctl(hEnet, gEthAppObj.coreId, CPSW_ALE_IOCTL_ADD_VLAN, &prms);
    if (status != ENET_SOK)
    {
    appLogPrintf("%s() failed ADD_VLAN ioctl failed: %d\n", __func__, status);
    }
    #endif

    polInArgs.policerMatch.policerMatchEnMask = 0U;

    /* Add policer entry for port 7 match */
    polInArgs.policerMatch.policerMatchEnMask = CPSW_ALE_POLICER_MATCH_PORT;
    polInArgs.policerMatch.portNum = CPSW_ALE_MACPORT_TO_ALEPORT(ENET_MAC_PORT_7);
    polInArgs.policerMatch.portIsTrunk = false;

    polInArgs.threadIdEn = true;
    polInArgs.threadId = flowId;
    polInArgs.peakRateInBitsPerSec = 0U;
    polInArgs.commitRateInBitsPerSec = 0U;

    ENET_IOCTL_SET_INOUT_ARGS(&prms, &polInArgs, &polOutArgs);

    status = Enet_ioctl(hEnet, gEthAppObj.coreId, CPSW_ALE_IOCTL_SET_POLICER, &prms);
    if (status != ENET_SOK)
    {
    appLogPrintf("Failed to register PORT 7 policer: %d\n", status);
    }
    if (status == ENET_SOK)
    {
    ENET_IOCTL_SET_NO_ARGS(&prms);
    status = Enet_ioctl(hEnet, gEthAppObj.coreId, CPSW_ALE_IOCTL_DUMP_TABLE, &prms);
    ENET_IOCTL_SET_NO_ARGS(&prms);
    status = Enet_ioctl(hEnet, gEthAppObj.coreId, CPSW_ALE_IOCTL_DUMP_POLICER_ENTRIES, &prms);
    }


    setRxFilter = CPSW_ALE_RXFILTER_ALL;
    ENET_IOCTL_SET_IN_ARGS(&prms, &setRxFilter);

    status = Enet_ioctl(hEnet, gEthAppObj.coreId, CPSW_ALE_IOCTL_SET_RX_FILTER, &prms);
    if (status != ENET_SOK)
    {
    appLogPrintf("rx filter Failed to register PORT 7 policer: %d\n", status);
    }

    return status;
    }

    Thanks and Regards,

    Venu. 

  • Hi,

    please check and correct us if any modification or fine tune required and we tested this any frame VLAN or Non VLAN or any random frames getting received in MCU2_1. 

    Setting Rx filter all will bypass ALE and pass all packets to Host Port from all external Ports, not only from Port-7.
    I hope this is not you required. Only Port-7 data sent to host port and then to mcu2_1.

    You can also perform below as well for your use-case:
    1. Configure Port-7 as MAC only Port and mapped to MCU2_1 client, which is supported in latest TI SDKs.
    2. In SDK 7.3 all are switch ports, and no MAC only Port configuration supported. You can make following change along with above Port-7 classifier.

    a) Update Port-7 as MAC only from CPSW ALE_PORTCTL0y_register (0x0C03E040+0x4*6)
    b) Also, enable copy all frames from MAC only to Host.


    Best Regards,
    Sudheer

  • Hi Sudheer,

    Can you please mention API name we need to use to set these registers.

    Thanks,
    Venu H

  • Hi,

    Can you please mention API name we need to use to set these registers.

    Make below as TRUE for port-7.
    ...

    You can set the same in "CpswAle_initCfg" API also only for Port-7 as per your interested port.

    Best Regards,
    Sudheer

  • Hi Sudheer,

    Currently we are testing with "Setting Rx filter all", 
    we are observing some issue with Ethertype and Payload.

    Ethertype is always reporting 0x8100 and extra 12 bytes are added in the payload.
    Can you please help to analyse this ? 

    Thanks,
    Venu H

  • Hi,

    As I have informed above, "setting Rx filter all" is not recommended.

    extra 12 bytes are added in the payload.

    If packet size is smaller then CPSW H/W append the dummy bytes to make packet size minimum of 64B.
    Ether Type 0x8100 might be because of packet is VLAN tagged

    Best Regards,
    Sudheer

  • Hi Sudheer,

    But if you see the above screenshot, Length reported from CPSW is 58 bytes, i mean only 12 bytes are added extra.

    But we didn't added VLAN tagging explicitly. May i know which function we need to check for VLAN tagging is done or not ?

    Thanks,
    Venu H

  • Hi,

    But if you see the above screenshot, Length reported from CPSW is 58 bytes, i mean only 12 bytes are added extra.

    But we didn't added VLAN tagging explicitly. May i know which function we need to check for VLAN tagging is done or not ?

    I could not find Eth_RxIndication API as captured in below. Might be added by your self. Please check how you are printing the information.

    If you don't mine, can you please point me the source code for above.

    You can all perform below as well for your use-case:
    1. Configure Port-7 as MAC only Port and mapped to MCU2_1 client, which is supported in latest TI SDKs.
    2. In SDK 7.3 all are switch ports, and no MAC only Port configuration supported. You can make following change along with above Port-7 classifier.

    a) Update Port-7 as MAC only from CPSW ALE_PORTCTL0y_register (0x0C03E040+0x4*6)
    b) Also, enable copy all frames from MAC only to Host.

    You can check the suggestion shared above.

    If you don't have any issue with /impact on other ports functionality, then it's your wish to use/configure however is working for you.


    Best Regards,
    Sudheer

  • Hi Sudheer,

    Lets focus on our use case only as you suggested.

    I added below code in "CpswAle_initCfg", Working as expected.
    I mean 2_1 is able to receive all the frames.

    Our original issue is solved now, Thanks for your help !!

      aleCfg->portCfg[7].macModeCfg.macOnlyCafEn = TRUE;
      aleCfg->portCfg[7].macModeCfg.macOnlyEn = TRUE; 

    Current issue we are seeing related to EtherType and payload.

    In Eth_irq.c file, we have interrupt processing Eth_RxIrqHdlr_0, it will call Eth_processRxPkt(),
    In turn it will call EthIf_RxIndication(), here i am printing the Data we received.

    FUNC(void, ETHIF_CODE) EthIf_RxIndication
    (
    VAR(uint8, AUTOMATIC) CtrlIdx,
    VAR(Eth_FrameType, AUTOMATIC) FrameType,
    VAR(boolean, AUTOMATIC) IsBroadcast,
    P2CONST(uint8, AUTOMATIC, ETHIF_APPL_DATA) SrcPhysAddrPtr,
    P2CONST(uint8, AUTOMATIC, ETHIF_APPL_DATA) DestPhysAddrPtr,
    #if(ETHIF_AR_VERSION_431 == ETHIF_ETH_AR_VERSION)
    P2CONST(Eth_DataType, AUTOMATIC, ETHIF_APPL_CONST) DataPtr,
    #else
    P2VAR(Eth_DataType, AUTOMATIC, ETHIF_APPL_DATA) DataPtr,
    #endif
    VAR(uint16, AUTOMATIC) LenByte
    )
    {
    uint8 *buf = (uint8 *)DataPtr;

    UART_printf("[Main2_1]Eth_RxIndication: len: %d, bcast: %s, EtherType: 0x%04x\n",
                                                                         LenByte, IsBroadcast ? "yes" : "no", FrameType & 0xFFFFU);


    UART_printf("[Main2_1]Src_MAC_addr: %x:%x:%x:%x:%x:%x,Dst_MAC_addr: %x:%x:%x:%x:%x:%x \n",
                                          SrcPhysAddrPtr[0],SrcPhysAddrPtr[1],SrcPhysAddrPtr[2],SrcPhysAddrPtr[3],SrcPhysAddrPtr[4],SrcPhysAddrPtr[5],
                                          DestPhysAddrPtr[0],DestPhysAddrPtr[1],DestPhysAddrPtr[2],DestPhysAddrPtr[3],DestPhysAddrPtr[4],DestPhysAddrPtr[5]);
    UART_printf("[Main2_1]EthApp: Eth_RxIndication contents are below\n");


    for(i = 1; i <= LenByte; i++)
    {
           UART_printf("0x%x ",buf[i-1]);
           if((i % 10) == 0)
           UART_printf("\n");
    }

    }

    We can have quick call to debug faster.

    Thanks,
    Venu H

  • Hi VENU,

    I added below code in "CpswAle_initCfg", Working as expected.
    I mean 2_1 is able to receive all the frames.

    Our original issue is solved now, Thanks for your help !!

      aleCfg->portCfg[7].macModeCfg.macOnlyCafEn = TRUE;
      aleCfg->portCfg[7].macModeCfg.macOnlyEn = TRUE; 

    Current issue we are seeing related to EtherType and payload.

    It is good to here that you use-case is achieved.
    Thanks for the update.

    In Eth_irq.c file, we have interrupt processing Eth_RxIrqHdlr_0, it will call Eth_processRxPkt(),
    In turn it will call EthIf_RxIndication(), here i am printing the Data we received.

    Can you please create a new thread related to this.

    Best Regards,
    Sudheer