AM625: Help setting PRUSS clock to 333MHz on AM6254

António Oliveira

Part Number: AM625
Other Parts Discussed in Thread: SK-AM62B-P1

Tool/software:

Hi all,

I'm trying to set the PRUSS core clock to 333 on an SK-AM62B-P1 board using information from the following pages:

* https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1048998/re-am6442-how-to-check-and-set-the-pru-core-frequency-in-linux

* https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1049800/faq-pru_icssg-how-to-check-and-set-pru-core-frequency-in-linux

Ultimately I went for using the following addition to `pruss_core_clk`:

&pruss_coreclk_mux {
	assigned-clocks = <&k3_clks 81 0>, <&pruss_coreclk_mux>;
	assigned-clock-parents = <&k3_clks 81 1>, <&k3_clks 81 20>;
	assigned-clock-rates = <333000000>;
};

`k3conf` seems to confirm that the PRU is running at 333MHz, but I'm not exactly sure of what to make of its output:

# k3conf dump clock 81

|------------------------------------------------------------------------------|
| VERSION INFO                                                                 |
|------------------------------------------------------------------------------|
| K3CONF | (version 0.3-nogit built Thu Jul 25 14:13:02 UTC 2024)              |
| SoC    | AM62X SR1.0                                                         |
| SYSFW  | ABI: 4.0 (firmware version 0x000a '10.1.1--v10.01.01 (Fiery Fox))') |
|------------------------------------------------------------------------------|

|-----------------------------------------------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name                                                             | Status          | Clock Frequency |
|-----------------------------------------------------------------------------------------------------------------------------------|
|    81     |     0    | DEV_ICSSM0_CORE_CLK                                                    | CLK_STATE_READY | 333333333       |
|    81     |     1    | DEV_ICSSM0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK           | CLK_STATE_READY | 333333333       |
|    81     |     2    | DEV_ICSSM0_CORE_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK          | CLK_STATE_READY | 333333333       |
|    81     |     3    | DEV_ICSSM0_IEP_CLK                                                     | CLK_STATE_READY | 250000000       |
|    81     |     4    | DEV_ICSSM0_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK           | CLK_STATE_READY | 250000000       |
|    81     |     5    | DEV_ICSSM0_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK           | CLK_STATE_READY | 200000000       |
|    81     |     6    | DEV_ICSSM0_IEP_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT           | CLK_STATE_READY | 0               |
|    81     |     8    | DEV_ICSSM0_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                  | CLK_STATE_READY | 0               |
|    81     |     9    | DEV_ICSSM0_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                      | CLK_STATE_READY | 0               |
|    81     |    10    | DEV_ICSSM0_IEP_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK  | CLK_STATE_READY | 400000000       |
|    81     |    11    | DEV_ICSSM0_IEP_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000       |
|    81     |    13    | DEV_ICSSM0_UCLK_CLK                                                    | CLK_STATE_READY | 192000000       |
|    81     |    14    | DEV_ICSSM0_VCLK_CLK                                                    | CLK_STATE_READY | 250000000       |
|-----------------------------------------------------------------------------------------------------------------------------------|

So I built a small firmware that just toggles a GPO at fixed rate (cycles):

    while (1 ) {
        __delay_cycles(100);
        __R30 |= 0x80;
        __delay_cycles(100);
        __R30 &= ~0x80;
    }

And measured the output with a scope.

What I found is that although `k3conf` follows the assigned-clock-rate that I set, the timings of the GPO remain unchanged, whereas I'd expect them to scale almost linearly with the configured PRU frequency (200, 250 or 333 MHz).

Even though this has been thoroughly covered in the links above I'm probably still missing some key to understand that information and need your help figuring this out.

Is my assumption that the loop above does not scale up in speed as we increase the PRU clock?

What is ` <&k3_clks 81 20>` ? I searched it in AM62X Clock Identifiers and couldn't find a description.

Finally, in addition to the increase of the clock to 333MHz, is it possible to enable spread spectrum on the input PLL?

Kind regards,

António

3 days ago

0 Nick Saulnier 2 days ago

TI__Guru* 88125 points

Hello António,

Apologies for the confusion here. We actually realized after SDK 10.0 that we were not setting the PRU clock properly - the clock setting in the Linux devicetree file was just a copy-paste of the default AM64x setting, and would throw a clock error. I filed a bug that we were planning to fix for the upcoming SDK 10.1. Let me check to see if the team actually resolved the bug, or if it is still outstanding...

The thread where this first came to my attention is here: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1410928/am625-sdk-10-ti-sci-clk-recalc-rate-failed-for-dev-81-clk-20-ret--19

I'll also link you to another thread with the same question. John is pretty smart and I won't have the bandwidth to run any tests on my end for the next couple of weeks, so he might come up with a solution before I can: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1450458/am625-pru-clock-speed

I'll update the thread when I hear back from the developers.

Regards,

Nick

+1 Nick Saulnier 1 day ago in reply to Nick Saulnier

TI__Guru* 88125 points

Ok, I asked the dev team to re-run the tests for this commit, and it DOES look like this gets rid of the clock errors on boot:
https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/commit/arch/arm64/boot/dts/ti/k3-am62-main.dtsi?h=ti-linux-6.6.y-cicd&id=34e6b1d215aae3e5d9c9d455edc943140ec99775

So you should be able to use this as a framework for changing the PRU clock frequency to 333MHz.

Please note that I expect the PRU clocking information presented in the Technical Reference Manual (TRM) is wrong. See the above thread for more details about how I expect the clocking to actually look like: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1410928/am625-sdk-10-ti-sci-clk-recalc-rate-failed-for-dev-81-clk-20-ret--19

Apologies in advance that I will not be able to devote much more time to this question for the next couple of weeks. Please do keep me updated though - I am the author of the AM62x academy's multicore module (I'll link that here in case you are doing any M4F or DM R5F development as well: https://dev.ti.com/tirex/explore/node?node=A__AJa64F6ctzZNbb.TYx4mCA__AM62-ACADEMY__uiYMDcq__LATEST). In 2025 the team and I will be creating a new module for the AM62x academy called the PRU academy. One of the pages I want to add is modifying the clock frequency, so I am bookmarking this thread as a reference when we get to writing that page.

Regards,

Nick

0 António Oliveira 1 day ago in reply to Nick Saulnier

Prodigy 95 points

Hi Nick,

As usual, your super useful insights helped me figure this out and reach a working solution. :)

As modified pruss_coreclock_mux as follows:

&pruss_coreclk_mux {
	clocks = <&k3_clks 81 0>,  /* pruss_core_clk */
				<&k3_clks 81 14>; /* pruss_iclk */
	assigned-clocks = <&pruss_coreclk_mux>;
	assigned-clock-parents = <&k3_clks 81 14>;
	assigned-clock-rates = <333333333>;
};

The system boots fine and running the square wave from the top post, yields a ~1.62MHz square wave (200 PRU cycles, give or take) which extrapolates to 333MHz.

Somewhat related to this, I'd like to understand if there's any possibility of enabling spread spectrum on this clock. Any hints about this would be trully appreciated.

Kind regards,

António

Processors

Processors forum

AM625: Help setting PRUSS clock to 333MHz on AM6254