66AK2G12: SOC to Codec connection and design verification

Avner

We will review the pdf and questions. However, it make take some time before I can provide an update.

--Paul 

Avner Cohen said:

Q1: please check correctness and remark on mistake or improvement

The audio implementation looks fine. Be careful on the 3 codec clock routing in order to avoid reflections.  You may consider adding a series 0R resistior to the bit clock line in case you do encounter reflections. 

Avner Cohen said:

Q2: the application note McASP Design Guide SPRACK0–January 2019  section 4.3 show different connection to codec, called sync mode. There the master of the bus is the codec. Buy in my design the master is the SOC. Therefore, the all the clocking signals: MCLK, BCLK, Frame-sync, are sourced from the SOC to the Codec and not vis a versa – is this OK?

This is fine. I see you are using an external source for you audio clock to achieve the desired bit sampling rate. I assume this works for both McASP configurations. 

Avner Cohen said:

Q3. The receive clocks are not connected at all – AHCLK, AFSR, ACLKR are floating with no connection. – is this ok ?

This is fine in your use case. However, you cannot leave pins floating. You must follow the guidance in the datasheet, section 4.5 Connections for Unused Pins.

Avner Cohen said:

Q4. Looking at the internal routing inside the SOC marked by green, show the path of clocks as I see it.  Is it correct ? Does the internal parts circled in red are indeed not used and the registers related to them actually are “don’t care”  emphasis on the receive section that is unused ?

Your green highlighted routing is valid.  The Red logic is not needed as it is part of the receive clock generation and not used in Sync mode. 

Avner Cohen said:

BQ1 : relating to first page showing the Ethernet PHY that uses 50Mhz clock. I would like to know if I can remove the 50Hz oscillator from the design: Is it possible to have the EMAC Ethernet clock Produced from the Core PLL which is 25Mhz and feed the PHY somehow with the 50Mhz CLKOUT generated inside the SOC to the PHY ?.   (with H23 pin out )

If yes, how to handle input pin  D24 RMII_REFCLK  which will be not connected to a clock?

I will have the relevant expert answer this question. 

--Paul 

Hi Paul,

Thanks for the answer. I wait for the last section that you said you need to check.

Regarding the unused McASP RX section, They do not appear in section 4.5 therefore I assume they can be treated as CMOS input/output ie. pull down for input and floating for output. (but then the direction needs to be defined)  So in order to even avoid adding resistors or setting direction, Is it possible to set the pins as GPIO using pinmux  (even though the  TX part is in use) thus avoiding pullup/down resistors?

That means that when setting it to GPIO some kind of internal pull is added automatically for the unused pin function.

For example setting the McASP0_ACLKR pin E9 which is bit clock as GPIO, Even though the TX of McASP0 is in use.   

Regards and happy holidays,

  Avner

  Hello Avner

Avner Cohen said:

BQ1 : relating to first page showing the Ethernet PHY that uses 50Mhz clock. I would like to know if I can remove the 50Hz oscillator from the design: Is it possible to have the EMAC Ethernet clock Produced from the Core PLL which is 25Mhz and feed the PHY somehow with the 50Mhz CLKOUT generated inside the SOC to the PHY ?.   (with H23 pin out )

Are you Ok to use a clock source example a crystal for the EPHY. If yes i can verify if the processor can work with the EPHY configured for master.

If not you may have to generate a 25M from the SOC, connect the clock to EPHY and use the output of the EPHY to the processor Ref clock. 

If case the processor is able to generate 50M you may still need buffer the clock inputs to the processor and EPHY individually.

Can you please let me know your approach to connect the EPHY and the processor for me to check further.

Regards,

Sreenivasa

Hi Sreenivasa,

Thanks for the answer and suggestions.

If I understand you correctly then in both options that you suggest, the RMII_REFCLK pin D24 must be connected to external clock even if the SOC can source the EMAC clocking from the internal core clock. Is that right?

Also If I move from RMII to MII then the pin D24 no longer needs external clocking. Is that right?

The project needs to be low cost. That was the reason I thought of removing the 50Mhz oscillator.

Actually the Ethernet in this project is only for Debug and software updates. The released product does not need to be with Ethernet. So, I thought of using the evaluation board DP83826-EVM-AM2 as standard card for the above purposes.(based on Ti DP83826 chip)

Q1) Does the Module DP83826-EVM-AM2 can work with my SOC 66AK2G12ABYT100 ?

Q2) Note that the connector is dictating the signals. So I can use Ither MII or RMII. So, If answer to Q1 is positive, How you suggest connecting it with the SOC?

Note that the module does not have Oscillator/Cristal assembled on it, though it has a place for it – so I would like to avoid soldering on it.

Does external module working in MII mode, without oscillator on the module nor attached to pin D24 and clock of 25M, sourced form the SOC pin H23 feeding the module, can be a solution to my needs?

(basing my assumption on section 5.9.3.8 in the DS : “CLKOUT port provides an option to output 50 MHz or 25 MHz clock. This clock can be used as a

reference clock for RMII or MII Ethernet companion devices.” )

Hello Avner

Thank you.

Avner Cohen said:

Also If I move from RMII to MII then the pin D24 no longer needs external clocking. Is that right?

This is correct.

Is there a MAC interface that you are considering to interface. based on the inputs i can check the feasibility.

Regards,

Hi Sreenivasa,

Since I am going to use the Ti Module DP83826-EVM-AM2 the Mac interface, as I mentioned it can be Ither RMII or MII. Whichever will be lower cost.

If you kindly reply to the question presented about the  RMII_REFCLK,    it will be clear to me to select the right one. Also I ask about the MII option using CLKOUT if you will check for that and answer about the feasibility and correctness , then we can say we have a solution.

I have added a schematic block diagram of the design with the DP83826-EVM-AM2 module connected to the soc 66AK2G12ABYT100 in MII mode.

The left side is the card with the SOC and the right side is the schematics of the module. In orange is the Module connector. Also its picture can be seen in the middle left.

Please check it and refer to the connections:

1. Pin D24 RMII_REFCLK is not used and not connected to clock è is it OK?
2. The CLKOUT pin H23 is used to output 25M using the internal dividers. See table at the bottom left side è is it feasible?
3. No Oscillators used (for Ethernet on the digital board and on the module) and clocking is based on the Core clock.
4. MII_TXER not connected.

Thanks,

Avner

see attachment:

  MII_piggyback_for_TI.pdf

Hello Avner

Thank you for the inputs.

Let me review and comeback.

Based on the inputs my quick understanding is - you are looking to implement ethernet interface with the DP83826 that does not use a crystal.

Regards,

Sreenivasa

Hi Sreenivasa,
You are correct. 

Looking forward for your answers.

Happy holidays,

  Avner