AM62A7: Does cadence OSPI controller support use PHY module in STIG or indirect read mode?

Hi,

I have read through your query, please read my comments below.

daniel zhang said:

• EVB: SK-AM62A-LP, replace the OSPI NAND Flash on board with OSPI NOR Flash
• OSPI NOR Flash EPN: MX66UW2G345G

It should not be a problem using a NOR Flash part like Macronix, but you have to consider the following.

In an Octal DDr flash, each word is 16bit and thus can have big vs little endianness.. macronix is big endian and our system is little endian. Controller doesn't provide a way to swap this. This is not a issue if we always stick to 8d-8d-8d mode for all data operations. But the moment you try mixed mode, this will hurt.

daniel zhang said:

The background information I know is that PHY can only be used in direct read/write mode.

1. And in pipeline mode only 16-byte aligned data can be read with PHY, but how to read non-aligned data correctly in case of 133MHz and DTR 8-IO without PHY?
2. TAP read delay can not meet the OSPI NOR Flash read timing requirement in 133MHz and DTR 8-IO condition.
3. Because read status register(RDSR) operation can only work in STIG mode, does the controller support use PHY in this mode?

If opting to choose Phy mode, then please read through this nicely written FAQ: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1431856/faq-am62a7-ospi-phy-tuning-algorithm

So currently for NOR Flash part: we support Direct Reads and Indirect Write.

and for NAND Flash part we support: Direct reads and Direct write operation. The reason for this is documented here: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1448730/am6421-does-ospi-support-dma/5561444#5561444

Regards,

Vaibhav

Hi, thank you for your reply.

1. First, MX66UW2G345G is new Macronix Octal Flash EPN, and can swap the byte by itself in DTR OPI read, it doesn't need controller to swap byte again. It output data in byte mode instead of word unit.
• Vaibhav Kumar said:

  So currently for NOR Flash part: we support Direct Reads and Indirect Write.
1. but I have a question, how can host read Flash status register (RDSR) correctly in 133MHz or higher frequency and DTR Octal mode without PHY. Without rx, tx, and read delay configuration parameter, can RDSR still read correctly?