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Tool/software:
Hi,
according to the DRA78x TRM sysboot[5] controls the ADC clock divider:
0: Divide by 2 (assuming SYS_CLK1 = 27MHz)
1: no division (assuming SYS_CLK1 up to 20MHz)
Our question is what would be the effect of having a SYS_CLK1 of 20MHz and at the same time having sysboot[5]=0?
Would it result in only the ADC_CLK to be slower or are there other side effects?
Moreover, is it possible to overwrite the divide by 2 in SW after booting?
The background is that we might have the issue that even though we have a pullup on sysboot[5] and a SYS_CLK1=20MHz, the sysboot[5] pin might be pulled low in some circumstances by other components on our PCB. Hence, the question whether there are any adverse side effects other than the ADC running at a slower clock.
As a side question: what is the influence of sysboot[6]?
The TRM only mentions that it is reserved and must be pulled low. Is it possible that it causes slow or delayed boot times?
BR,
Jacob
