Original question:
DRA821U: DRA821U CPSW5G Ethernet native mode support for GESI board
Tool/software:
Champ,
My customer is about to use RGMii 2, RGMii 3 and RGMii 4 for three Ethernet port on DRA821 because there are only two SERDES and PCIe and USB will take two of them.
Customer would like to have patch to enable RGMii 2 on DRA821 EVM with GESI board as reference to enable all the three RGMii ports.
BR, Rich
Hi Rich,
I have enabled RGMII2 from Linux and able to communicate with remote device.
Please find the below logs and code reference for enabling RGMII from Native Linux Diver.
k3-j7200-evm-quad-port-eth-exp.dtso file:
https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/k3_2D00_j7200_2D00_evm_2D00_quad_2D00_port_2D00_eth_2D00_exp.dtso
k3-j7200-common-proc-board.dts file:
Test Log:
Ping test log fro your reference
Note:
As TI EVM supports only RGMII2, above dtso configured RGMII2 pins alone but for reference provided configuration information for all CPSW Ports.
Best Regards,
Sudheer
Hi Ti
I apply the rgmii patch .
eth1 from A72 rgmii works test by ping command. But iperf test fail
Hi
patch . But if still do not work by 1G speed.
And I have a new question , how to enable this RGMII port in uboot???
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-moxa-uc-8600a.dts b/arch/arm64/boot/dts/ti/k3-j7200-moxa-uc-8600a.dts
index 7a3a9188c..d9bbe3ddc 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-moxa-uc-8600a.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-moxa-uc-8600a.dts
@@ -433,6 +433,7 @@
cpsw5g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,min-output-impedance;
@@ -457,7 +458,7 @@
&cpsw0_port1 {
status = "disabled";
phy-handle = <&cpsw5g_phy1>;
- phy-mode = "rgmii-rxid";
+ phy-mode = "rgmii-id";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 1>;
};
diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
index 81dd1c344..e4965439d 100644
--- a/drivers/phy/ti/phy-gmii-sel.c
+++ b/drivers/phy/ti/phy-gmii-sel.c
@@ -210,20 +210,29 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_soc_dm814 = {
static const
struct reg_field phy_gmii_sel_fields_am654[][PHY_GMII_SEL_LAST] = {
- { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x0, 0, 2), },
- { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x4, 0, 2), },
- { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x8, 0, 2), },
- { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0xC, 0, 2), },
- { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x10, 0, 2), },
- { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x14, 0, 2), },
- { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x18, 0, 2), },
- { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x1C, 0, 2), },
+ { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x0, 0, 2),
+ [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x0, 4, 4), },
+ { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x4, 0, 2),
+ [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x4, 4, 4), },
+ { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x8, 0, 2),
+ [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x8, 4, 4), },
+ { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0xC, 0, 2),
+ [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0xC, 4, 4), },
+ { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x10, 0, 2),
+ [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x10, 4, 4), },
+ { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x14, 0, 2),
+ [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x14, 4, 4), },
+ { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x18, 0, 2),
+ [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x18, 4, 4), },
+ { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x1C, 0, 2),
+ [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x1C, 4, 4), },
};
static const
struct phy_gmii_sel_soc_data phy_gmii_sel_soc_am654 = {
.use_of_data = true,
.regfields = phy_gmii_sel_fields_am654,
+ .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE),
};
static const
@@ -231,6 +240,7 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = {
.use_of_data = true,
.regfields = phy_gmii_sel_fields_am654,
.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
+ .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE),
.num_ports = 4,
.num_qsgmii_main_ports = 1,
};
@@ -240,6 +250,7 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = {
.use_of_data = true,
.regfields = phy_gmii_sel_fields_am654,
.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
+ .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE),
.num_ports = 8,
.num_qsgmii_main_ports = 2,
};
@@ -251,6 +262,7 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = {
.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) |
BIT(PHY_INTERFACE_MODE_USXGMII),
.num_ports = 8,
+ .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE),
.num_qsgmii_main_ports = 2,
};
Hi
Whether you have any finding so this?I need to check iperf with 1 Gbps, after adjusting the PHY delays.
I have tested with delay adjustment at PHY side and disabled delay from MAC side, ieprf is running at 1 Gbps successfully.
Please refer to the below capture for more information.
Device tree configuration for your reference.
Best Regards,
Sudheer